113 lines
5.8 KiB
C
113 lines
5.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __A9_H
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#define __A9_H
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int a9_clk_init(void);
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void a9_clk_exit(void);
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int a9_aoclk_init(void);
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void a9_aoclk_exit(void);
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#define ANACTRL_GP0PLL_CTRL0 (0x0080 << 2)
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#define ANACTRL_GP0PLL_CTRL1 (0x0081 << 2)
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#define ANACTRL_GP0PLL_CTRL2 (0x0082 << 2)
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#define ANACTRL_GP0PLL_CTRL3 (0x0083 << 2)
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#define ANACTRL_HIFI0PLL_CTRL0 (0x00a0 << 2)
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#define ANACTRL_HIFI0PLL_CTRL1 (0x00a1 << 2)
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#define ANACTRL_HIFI0PLL_CTRL2 (0x00a2 << 2)
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#define ANACTRL_HIFI0PLL_CTRL3 (0x00a3 << 2)
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#define ANACTRL_HIFI1PLL_CTRL0 (0x00a8 << 2)
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#define ANACTRL_HIFI1PLL_CTRL1 (0x00a9 << 2)
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#define ANACTRL_HIFI1PLL_CTRL2 (0x00aa << 2)
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#define ANACTRL_HIFI1PLL_CTRL3 (0x00ab << 2)
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#define ANACTRL_CSIPLL_CTRL0 (0x00cc << 2)
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#define ANACTRL_CSIPLL_CTRL1 (0x00cd << 2)
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#define ANACTRL_CSIPLL_CTRL2 (0x00ce << 2)
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#define ANACTRL_CSIPLL_CTRL3 (0x00cf << 2)
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#define ANACTRL_CSIPLL_CTRL4 (0x00d0 << 2)
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#define ANACTRL_CSIPLL_CTRL5 (0x00d1 << 2)
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#define ANACTRL_CSIPLL_CTRL6 (0x00d2 << 2)
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#define ANACTRL_CSIPLL_CTRL7 (0x00d3 << 2)
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#define ANACTRL_CSIPLL_CTRL8 (0x00d4 << 2)
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#define ANACTRL_CSIPLL_CTRL9 (0x00d5 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG0 (0x008c << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG1 (0x008d << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG2 (0x008e << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG3 (0x008f << 2)
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#define CLKCTRL_SD_EMMC_CLK_CTRL0 (0x00a4 << 2)
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#define CLKCTRL_SD_EMMC_CLK_CTRL1 (0x00a5 << 2)
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#define CLKCTRL_PWM_CLK_H_CTRL (0x00af << 2)
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#define CLKCTRL_PWM_CLK_I_CTRL (0x00b0 << 2)
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#define CLKCTRL_PWM_CLK_J_CTRL (0x00b1 << 2)
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#define CLKCTRL_PWM_CLK_K_CTRL (0x00b2 << 2)
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#define CLKCTRL_PWM_CLK_L_CTRL (0x00b3 << 2)
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#define CLKCTRL_PWM_CLK_M_CTRL (0x00b4 << 2)
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#define CLKCTRL_PWM_CLK_N_CTRL (0x00b5 << 2)
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#define CLKCTRL_SPISG_CLK_CTRL (0x00c0 << 2)
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#define CLKCTRL_SPISG_CLK_CTRL1 (0x00c1 << 2)
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#define CLKCTRL_SAR_CLK_CTRL0 (0x00d4 << 2)
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#define CLKCTRL_AMFC_CLK_CTRL (0x00d5 << 2)
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#define CLKCTRL_NNA_CLK_CTRL (0x00d7 << 2)
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#define CLKCTRL_USB_CLK_CTRL (0x00d8 << 2)
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#define CLKCTRL_PCIE_CLK_CTRL (0x00d9 << 2)
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#define CLKCTRL_CMPR_CLK_CTRL (0x00da << 2)
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#define CLKCTRL_DEWARPA_CLK_CTRL (0x00db << 2)
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#define CLKCTRL_SC_CLK_CTRL (0x00dc << 2)
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#define CLKCTRL_DPTX_CLK_CTRL (0x00de << 2)
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#define CLKCTRL_ISP0_CLK_CTRL (0x00df << 2)
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#define CLKCTRL_CVE_CLK_CTRL (0x00e0 << 2)
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#define CLKCTRL_PP_CLK_CTRL (0x00e1 << 2)
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#define CLKCTRL_GLBCLK_CTRL (0x00e2 << 2)
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#define CLKCTRL_USB_CLK_CTRL0 (0x00e3 << 2)
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#define CLKCTRL_USB_CLK_CTRL1 (0x00e4 << 2)
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#define CLKCTRL_CAN_CLK_CTRL0 (0x00e5 << 2)
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#define CLKCTRL_CAN_CLK_CTRL1 (0x00e6 << 2)
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#define CLKCTRL_I3C_CLK_CTRL (0x00e7 << 2)
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#define CLKCTRL_TS_CLK_CTRL (0x00e8 << 2)
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#define CLKCTRL_ETH_CLK_CTRL (0x00e9 << 2)
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#define CLKCTRL_GEN_CLK_CTRL (0x00ea << 2)
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#define CLKCTRL_MALI_CLK_CTRL (0x0100 << 2)
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#define CLKCTRL_MALI_STACK_CLK_CTRL (0x0101 << 2)
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#define CLKCTRL_DSPA_CLK_CTRL0 (0x0108 << 2)
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#define CLKCTRL_HEVCF_CLK_CTRL (0x0110 << 2)
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#define CLKCTRL_HCODEC_CLK_CTRL (0x0111 << 2)
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#define CLKCTRL_VPU_CLK_CTRL (0x0118 << 2)
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#define CLKCTRL_VAPBCLK_CTRL (0x011a << 2)
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#define CLKCTRL_VPU_CLKB_CTRL (0x0120 << 2)
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#define CLKCTRL_HDMI_CLK_CTRL (0x0121 << 2)
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#define CLKCTRL_HTX_CLK_CTRL0 (0x0123 << 2)
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#define CLKCTRL_HTX_CLK_CTRL1 (0x0124 << 2)
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#define CLKCTRL_HRX_CLK_CTRL0 (0x0125 << 2)
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#define CLKCTRL_HRX_CLK_CTRL1 (0x0126 << 2)
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#define CLKCTRL_HRX_CLK_CTRL2 (0x0127 << 2)
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#define CLKCTRL_HRX_CLK_CTRL3 (0x0128 << 2)
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#define CLKCTRL_VID_LOCK_CLK_CTRL (0x0129 << 2)
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#define CLKCTRL_VDIN_MEAS_CLK_CTRL (0x012a << 2)
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#define CLKCTRL_VID_CLK_CTRL (0x0130 << 2)
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#define CLKCTRL_VID_CLK_CTRL2 (0x0131 << 2)
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#define CLKCTRL_VID_CLK_DIV (0x0132 << 2)
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#define CLKCTRL_VIID_CLK_DIV (0x0133 << 2)
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#define CLKCTRL_VIID_CLK_CTRL (0x0134 << 2)
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#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL (0x0138 << 2)
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#define CLKCTRL_DSI_MEAS_CLK_CTRL (0x013d << 2)
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#define AO_CLKCTRL_OSCIN_CTRL (0x0000 << 2)
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#define AO_CLKCTRL_RTC_SYS_CLK0 (0x0001 << 2)
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#define AO_CLKCTRL_PWM_CLK_A_CTRL (0x0007 << 2)
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#define AO_CLKCTRL_PWM_CLK_B_CTRL (0x0008 << 2)
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#define AO_CLKCTRL_PWM_CLK_C_CTRL (0x0009 << 2)
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#define AO_CLKCTRL_PWM_CLK_D_CTRL (0x000a << 2)
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#define AO_CLKCTRL_PWM_CLK_E_CTRL (0x000b << 2)
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#define AO_CLKCTRL_PWM_CLK_F_CTRL (0x000c << 2)
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#define AO_CLKCTRL_PWM_CLK_G_CTRL (0x000d << 2)
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#define AO_CLKCTRL_CECB_CTRL0 (0x000e << 2)
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#define AO_CLKCTRL_CECB_CTRL1 (0x000f << 2)
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#define AO_CLKCTRL_RTC_BY_OSCIN_CTRL0 (0x0014 << 2)
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#define AO_CLKCTRL_RTC_BY_OSCIN_CTRL1 (0x0015 << 2)
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#endif /* __A9_H */
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