545 lines
16 KiB
C
545 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 - Google LLC
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* Author: Quentin Perret <[email protected]>
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* Author: Fuad Tabba <[email protected]>
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*/
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#ifndef __ARM64_KVM_PKVM_H__
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#define __ARM64_KVM_PKVM_H__
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#include <linux/arm_ffa.h>
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#include <linux/memblock.h>
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#include <linux/scatterlist.h>
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#include <asm/kvm_pgtable.h>
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#include <asm/sysreg.h>
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/* Maximum number of VMs that can co-exist under pKVM. */
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#define KVM_MAX_PVMS 255
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#define HYP_MEMBLOCK_REGIONS 128
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#define PVMFW_INVALID_LOAD_ADDR (-1)
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int pkvm_vm_ioctl_enable_cap(struct kvm *kvm,struct kvm_enable_cap *cap);
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int pkvm_init_host_vm(struct kvm *kvm, unsigned long type);
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int pkvm_create_hyp_vm(struct kvm *kvm);
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void pkvm_destroy_hyp_vm(struct kvm *kvm);
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bool pkvm_is_hyp_created(struct kvm *kvm);
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int pkvm_create_hyp_vcpu(struct kvm_vcpu *vcpu);
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void pkvm_host_reclaim_page(struct kvm *host_kvm, phys_addr_t ipa);
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int pvkm_enable_smc_forwarding(struct file *kvm_file);
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/*
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* This functions as an allow-list of protected VM capabilities.
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* Features not explicitly allowed by this function are denied.
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*/
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static inline bool kvm_pvm_ext_allowed(long ext)
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{
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switch (ext) {
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case KVM_CAP_IRQCHIP:
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case KVM_CAP_ONE_REG:
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case KVM_CAP_ARM_PSCI:
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case KVM_CAP_ARM_PSCI_0_2:
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case KVM_CAP_NR_VCPUS:
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case KVM_CAP_MAX_VCPUS:
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case KVM_CAP_MAX_VCPU_ID:
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case KVM_CAP_MSI_DEVID:
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case KVM_CAP_ARM_VM_IPA_SIZE:
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case KVM_CAP_ARM_PMU_V3:
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case KVM_CAP_ARM_SVE:
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case KVM_CAP_ARM_PTRAUTH_ADDRESS:
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case KVM_CAP_ARM_PTRAUTH_GENERIC:
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case KVM_CAP_ARM_PROTECTED_VM:
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return true;
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default:
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return false;
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}
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}
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static inline unsigned long pvm_supported_vcpu_features(void)
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{
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unsigned long features = 0;
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set_bit(KVM_ARM_VCPU_POWER_OFF, &features);
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if (kvm_pvm_ext_allowed(KVM_CAP_ARM_EL1_32BIT))
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set_bit(KVM_ARM_VCPU_EL1_32BIT, &features);
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if (kvm_pvm_ext_allowed(KVM_CAP_ARM_PSCI_0_2))
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set_bit(KVM_ARM_VCPU_PSCI_0_2, &features);
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if (kvm_pvm_ext_allowed(KVM_CAP_ARM_PMU_V3))
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set_bit(KVM_ARM_VCPU_PMU_V3, &features);
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if (kvm_pvm_ext_allowed(KVM_CAP_ARM_SVE))
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set_bit(KVM_ARM_VCPU_SVE, &features);
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if (kvm_pvm_ext_allowed(KVM_CAP_ARM_PTRAUTH_ADDRESS) &&
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kvm_pvm_ext_allowed(KVM_CAP_ARM_PTRAUTH_GENERIC)) {
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set_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, &features);
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set_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, &features);
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}
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return features;
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}
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/* All HAFGRTR_EL2 bits are AMU */
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#define HAFGRTR_AMU __HAFGRTR_EL2_MASK
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#define PVM_HAFGRTR_EL2_SET \
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(kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP) ? 0ULL : HAFGRTR_AMU)
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#define PVM_HAFGRTR_EL2_CLR (0ULL)
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/* No support for debug, trace, of PMU for protected VMs */
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#define PVM_HDFGRTR_EL2_SET __HDFGRTR_EL2_MASK
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#define PVM_HDFGRTR_EL2_CLR __HDFGRTR_EL2_nMASK
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#define PVM_HDFGWTR_EL2_SET __HDFGWTR_EL2_MASK
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#define PVM_HDFGWTR_EL2_CLR __HDFGWTR_EL2_nMASK
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#define HFGxTR_RAS_IMP (\
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HFGxTR_EL2_ERXADDR_EL1 | \
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HFGxTR_EL2_ERXPFGF_EL1 | \
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HFGxTR_EL2_ERXMISCn_EL1 | \
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HFGxTR_EL2_ERXSTATUS_EL1 | \
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HFGxTR_EL2_ERXCTLR_EL1 | \
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HFGxTR_EL2_ERXFR_EL1 | \
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HFGxTR_EL2_ERRSELR_EL1 | \
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HFGxTR_EL2_ERRIDR_EL1 \
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)
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#define HFGxTR_RAS_V1P1 (\
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HFGxTR_EL2_ERXPFGCDN_EL1 | \
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HFGxTR_EL2_ERXPFGCTL_EL1 \
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)
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#define HFGxTR_GIC HFGxTR_EL2_ICC_IGRPENn_EL1
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#define HFGxTR_CSV2 (\
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HFGxTR_EL2_SCXTNUM_EL0 | \
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HFGxTR_EL2_SCXTNUM_EL1 \
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)
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#define HFGxTR_LOR (\
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HFGxTR_EL2_LORSA_EL1 | \
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HFGxTR_EL2_LORN_EL1 | \
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HFGxTR_EL2_LORID_EL1 | \
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HFGxTR_EL2_LOREA_EL1 | \
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HFGxTR_EL2_LORC_EL1 \
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)
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#define HFGxTR_PAUTH (\
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HFGxTR_EL2_APIBKey | \
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HFGxTR_EL2_APIAKey | \
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HFGxTR_EL2_APGAKey | \
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HFGxTR_EL2_APDBKey | \
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HFGxTR_EL2_APDAKey \
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)
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#define HFGxTR_nAIE (\
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HFGxTR_EL2_nAMAIR2_EL1 | \
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HFGxTR_EL2_nMAIR2_EL1 \
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)
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#define HFGxTR_nS2POE HFGxTR_EL2_nS2POR_EL1
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#define HFGxTR_nS1POE (\
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HFGxTR_EL2_nPOR_EL1 | \
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HFGxTR_EL2_nPOR_EL0 \
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)
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#define HFGxTR_nS1PIE (\
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HFGxTR_EL2_nPIR_EL1 | \
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HFGxTR_EL2_nPIRE0_EL1 \
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)
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#define HFGxTR_nTHE HFGxTR_EL2_nRCWMASK_EL1
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#define HFGxTR_nSME (\
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HFGxTR_EL2_nTPIDR2_EL0 | \
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HFGxTR_EL2_nSMPRI_EL1 \
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)
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#define HFGxTR_nGCS (\
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HFGxTR_EL2_nGCS_EL1 | \
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HFGxTR_EL2_nGCS_EL0 \
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)
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#define HFGxTR_nLS64 HFGxTR_EL2_nACCDATA_EL1
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#define PVM_HFGXTR_EL2_SET \
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(kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP) ? 0ULL : HFGxTR_RAS_IMP) | \
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(kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) ? 0ULL : HFGxTR_RAS_V1P1) | \
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(kvm_has_feat(kvm, ID_AA64PFR0_EL1, GIC, IMP) ? 0ULL : HFGxTR_GIC) | \
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(kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, IMP) ? 0ULL : HFGxTR_CSV2) | \
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(kvm_has_feat(kvm, ID_AA64MMFR1_EL1, LO, IMP) ? 0ULL : HFGxTR_LOR) | \
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(vcpu_has_ptrauth(vcpu) ? 0ULL : HFGxTR_PAUTH) | \
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(vcpu_has_ptrauth(vcpu) ? 0ULL : HFGxTR_PAUTH) | \
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0
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#define PVM_HFGXTR_EL2_CLR \
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(kvm_has_feat(kvm, ID_AA64MMFR3_EL1, AIE, IMP) ? 0ULL : HFGxTR_nAIE) | \
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(kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S2POE, IMP) ? 0ULL : HFGxTR_nS2POE) | \
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(kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP) ? 0ULL : HFGxTR_nS1POE) | \
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(kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP) ? 0ULL : HFGxTR_nS1PIE) | \
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(kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP) ? 0ULL : HFGxTR_nTHE) | \
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(kvm_has_feat(kvm, ID_AA64PFR1_EL1, SME, IMP) ? 0ULL : HFGxTR_nSME) | \
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(kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP) ? 0ULL : HFGxTR_nGCS) | \
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(kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64) ? 0ULL : HFGxTR_nLS64) | \
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0
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#define PVM_HFGRTR_EL2_SET PVM_HFGXTR_EL2_SET
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#define PVM_HFGWTR_EL2_SET PVM_HFGXTR_EL2_SET
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#define PVM_HFGRTR_EL2_CLR PVM_HFGXTR_EL2_CLR
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#define PVM_HFGWTR_EL2_CLR PVM_HFGXTR_EL2_CLR
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#define HFGITR_SPECRES (\
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HFGITR_EL2_CPPRCTX | \
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HFGITR_EL2_DVPRCTX | \
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HFGITR_EL2_CFPRCTX \
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)
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#define HFGITR_TLBIOS (\
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HFGITR_EL2_TLBIVAALE1OS | \
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HFGITR_EL2_TLBIVALE1OS | \
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HFGITR_EL2_TLBIVAAE1OS | \
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HFGITR_EL2_TLBIASIDE1OS | \
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HFGITR_EL2_TLBIVAE1OS | \
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HFGITR_EL2_TLBIVMALLE1OS \
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)
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#define HFGITR_TLBIRANGE \
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(\
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HFGITR_TLBIOS | \
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HFGITR_EL2_TLBIRVAALE1 | \
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HFGITR_EL2_TLBIRVALE1 | \
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HFGITR_EL2_TLBIRVAAE1 | \
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HFGITR_EL2_TLBIRVAE1 | \
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HFGITR_EL2_TLBIRVAE1 | \
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HFGITR_EL2_TLBIRVAALE1IS | \
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HFGITR_EL2_TLBIRVALE1IS | \
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HFGITR_EL2_TLBIRVAAE1IS | \
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HFGITR_EL2_TLBIRVAE1IS | \
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HFGITR_EL2_TLBIVAALE1IS | \
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HFGITR_EL2_TLBIVALE1IS | \
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HFGITR_EL2_TLBIVAAE1IS | \
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HFGITR_EL2_TLBIASIDE1IS | \
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HFGITR_EL2_TLBIVAE1IS | \
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HFGITR_EL2_TLBIVMALLE1IS | \
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HFGITR_EL2_TLBIRVAALE1OS | \
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HFGITR_EL2_TLBIRVALE1OS | \
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HFGITR_EL2_TLBIRVAAE1OS | \
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HFGITR_EL2_TLBIRVAE1OS \
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)
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#define HFGITR_TLB HFGITR_TLBIRANGE
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#define HFGITR_PAN2 (\
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HFGITR_EL2_ATS1E1WP | \
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HFGITR_EL2_ATS1E1RP | \
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HFGITR_EL2_ATS1E0W | \
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HFGITR_EL2_ATS1E0R | \
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HFGITR_EL2_ATS1E1W | \
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HFGITR_EL2_ATS1E1R \
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)
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#define HFGITR_PAN HFGITR_PAN2
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#define HFGITR_DPB2 HFGITR_EL2_DCCVADP
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#define HFGITR_DPB_IMP HFGITR_EL2_DCCVAP
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#define HFGITR_DPB (HFGITR_DPB_IMP | HFGITR_DPB2)
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#define HFGITR_nGCS (\
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HFGITR_EL2_nGCSEPP | \
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HFGITR_EL2_nGCSSTR_EL1 | \
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HFGITR_EL2_nGCSPUSHM_EL1 \
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)
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#define HFGITR_nBRBE (\
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HFGITR_EL2_nBRBIALL | \
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HFGITR_EL2_nBRBINJ \
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)
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#define PVM_HFGITR_EL2_SET \
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(kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP) ? 0ULL : HFGITR_EL2_ATS1E1A) | \
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(kvm_has_feat(kvm, ID_AA64ISAR1_EL1, SPECRES, IMP) ? 0ULL : HFGITR_SPECRES) | \
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(kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS) ? 0ULL : HFGITR_TLB) | \
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(kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, IMP) ? 0ULL : HFGITR_PAN) | \
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(kvm_has_feat(kvm, ID_AA64ISAR1_EL1, DPB, IMP) ? 0ULL : HFGITR_DPB) | \
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0
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#define PVM_HFGITR_EL2_CLR \
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(kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP) ? 0ULL : HFGITR_nGCS) | \
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(kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP) ? 0ULL : HFGITR_nBRBE) | \
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0
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#define HCRX_NMI HCRX_EL2_TALLINT
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#define HCRX_nPAuth_LR HCRX_EL2_PACMEn
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#define HCRX_nFPMR HCRX_EL2_EnFPM
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#define HCRX_nGCS HCRX_EL2_GCSEn
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#define HCRX_nSYSREG128 HCRX_EL2_EnIDCP128
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#define HCRX_nADERR HCRX_EL2_EnSDERR
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#define HCRX_nDoubleFault2 HCRX_EL2_TMEA
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#define HCRX_nANERR HCRX_EL2_EnSNERR
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#define HCRX_nD128 HCRX_EL2_D128En
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#define HCRX_nTHE HCRX_EL2_PTTWI
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#define HCRX_nSCTLR2 HCRX_EL2_SCTLR2En
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#define HCRX_nTCR2 HCRX_EL2_TCR2En
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#define HCRX_nMOPS (HCRX_EL2_MSCEn | HCRX_EL2_MCE2)
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#define HCRX_nCMOW HCRX_EL2_CMOW
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#define HCRX_nNMI (HCRX_EL2_VFNMI | HCRX_EL2_VINMI)
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#define HCRX_SME HCRX_EL2_SMPME
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#define HCRX_nXS (HCRX_EL2_FGTnXS | HCRX_EL2_FnXS)
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#define HCRX_nLS64 (HCRX_EL2_EnASR| HCRX_EL2_EnALS | HCRX_EL2_EnAS0)
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#define PVM_HCRX_EL2_SET \
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(kvm_has_feat(kvm, ID_AA64PFR1_EL1, NMI, IMP) ? 0ULL : HCRX_NMI) | \
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(kvm_has_feat(kvm, ID_AA64PFR1_EL1, SME, IMP) ? 0ULL : HCRX_SME) | \
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0
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#define PVM_HCRX_EL2_CLR \
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(vcpu_has_ptrauth(vcpu) ? HCRX_nPAuth_LR : 0ULL) | \
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(kvm_has_feat(kvm, ID_AA64PFR1_EL1, GCS, IMP) ? 0ULL : HCRX_nGCS) | \
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(kvm_has_feat(kvm, ID_AA64ISAR2_EL1, SYSREG_128, IMP) ? 0ULL : HCRX_nSYSREG128) | \
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(kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ADERR, FEAT_ADERR) ? 0ULL : HCRX_nADERR) | \
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(kvm_has_feat(kvm, ID_AA64PFR1_EL1, DF2, IMP) ? 0ULL : HCRX_nDoubleFault2) | \
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(kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ANERR, FEAT_ANERR) ? 0ULL : HCRX_nANERR) | \
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(true /* trap unless ID_AA64MMFR0_EL1 PARANGE == 0b111 */ ? 0ULL : HCRX_nD128) | \
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(kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP) ? 0ULL : HCRX_nTHE) | \
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(kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SCTLRX, IMP) ? 0ULL : HCRX_nSCTLR2) | \
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(kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP) ? 0ULL : HCRX_nTCR2) | \
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(kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP) ? 0ULL : HCRX_nMOPS) | \
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(kvm_has_feat(kvm, ID_AA64MMFR1_EL1, CMOW, IMP) ? 0ULL : HCRX_nCMOW) | \
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(kvm_has_feat(kvm, ID_AA64PFR1_EL1, NMI, IMP) ? 0ULL : HCRX_nNMI) | \
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(kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP) ? 0ULL : HCRX_nXS) | \
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(kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64) ? 0ULL : HCRX_nLS64) | \
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0
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enum pkvm_moveable_reg_type {
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PKVM_MREG_MEMORY,
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PKVM_MREG_PROTECTED_RANGE,
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PKVM_MREG_ASSIGN_MMIO,
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};
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struct pkvm_moveable_reg {
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phys_addr_t start;
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u64 size;
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enum pkvm_moveable_reg_type type;
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};
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#define PKVM_NR_MOVEABLE_REGS 512
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extern struct pkvm_moveable_reg kvm_nvhe_sym(pkvm_moveable_regs)[];
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extern unsigned int kvm_nvhe_sym(pkvm_moveable_regs_nr);
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extern struct memblock_region kvm_nvhe_sym(hyp_memory)[];
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extern unsigned int kvm_nvhe_sym(hyp_memblock_nr);
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extern phys_addr_t kvm_nvhe_sym(pvmfw_base);
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extern phys_addr_t kvm_nvhe_sym(pvmfw_size);
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static inline unsigned long
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hyp_vmemmap_memblock_size(struct memblock_region *reg, size_t vmemmap_entry_size)
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{
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unsigned long nr_pages = reg->size >> PAGE_SHIFT;
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unsigned long start, end;
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start = (reg->base >> PAGE_SHIFT) * vmemmap_entry_size;
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end = start + nr_pages * vmemmap_entry_size;
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start = ALIGN_DOWN(start, PAGE_SIZE);
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end = ALIGN(end, PAGE_SIZE);
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return end - start;
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}
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static inline unsigned long hyp_vmemmap_pages(size_t vmemmap_entry_size)
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{
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unsigned long res = 0, i;
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for (i = 0; i < kvm_nvhe_sym(hyp_memblock_nr); i++) {
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res += hyp_vmemmap_memblock_size(&kvm_nvhe_sym(hyp_memory)[i],
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vmemmap_entry_size);
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}
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return res >> PAGE_SHIFT;
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}
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static inline unsigned long hyp_vm_table_pages(void)
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{
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return PAGE_ALIGN(KVM_MAX_PVMS * sizeof(void *)) >> PAGE_SHIFT;
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}
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static inline unsigned long __hyp_pgtable_max_pages(unsigned long nr_pages)
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{
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unsigned long total = 0;
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int i;
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/* Provision the worst case scenario */
|
|
for (i = KVM_PGTABLE_FIRST_LEVEL; i <= KVM_PGTABLE_LAST_LEVEL; i++) {
|
|
nr_pages = DIV_ROUND_UP(nr_pages, PTRS_PER_PTE);
|
|
total += nr_pages;
|
|
}
|
|
|
|
return total;
|
|
}
|
|
|
|
static inline unsigned long __hyp_pgtable_moveable_regs_pages(void)
|
|
{
|
|
unsigned long res = 0, i;
|
|
|
|
/* Cover all of moveable regions with page-granularity */
|
|
for (i = 0; i < kvm_nvhe_sym(pkvm_moveable_regs_nr); i++) {
|
|
struct pkvm_moveable_reg *reg = &kvm_nvhe_sym(pkvm_moveable_regs)[i];
|
|
res += __hyp_pgtable_max_pages(reg->size >> PAGE_SHIFT);
|
|
}
|
|
|
|
return res;
|
|
}
|
|
|
|
extern u64 kvm_nvhe_sym(hyp_lm_size_mb);
|
|
|
|
static inline unsigned long hyp_s1_pgtable_pages(void)
|
|
{
|
|
unsigned long res;
|
|
|
|
if (!kvm_nvhe_sym(hyp_lm_size_mb))
|
|
res = __hyp_pgtable_moveable_regs_pages();
|
|
else
|
|
res = __hyp_pgtable_max_pages(kvm_nvhe_sym(hyp_lm_size_mb) * SZ_1M / PAGE_SIZE);
|
|
|
|
/* Allow 1 GiB for private mappings */
|
|
res += __hyp_pgtable_max_pages(SZ_1G >> PAGE_SHIFT);
|
|
|
|
return res;
|
|
}
|
|
|
|
static inline unsigned long host_s2_pgtable_pages(void)
|
|
{
|
|
unsigned long res;
|
|
|
|
/*
|
|
* Include an extra 16 pages to safely upper-bound the worst case of
|
|
* concatenated pgds.
|
|
*/
|
|
res = __hyp_pgtable_moveable_regs_pages() + 16;
|
|
|
|
/* Allow 1 GiB for non-moveable regions */
|
|
res += __hyp_pgtable_max_pages(SZ_1G >> PAGE_SHIFT);
|
|
|
|
return res;
|
|
}
|
|
|
|
#ifdef CONFIG_PKVM_SELFTESTS
|
|
static inline unsigned long pkvm_selftest_pages(void) { return 32; }
|
|
#else
|
|
static inline unsigned long pkvm_selftest_pages(void) { return 0; }
|
|
#endif
|
|
|
|
#define KVM_FFA_MBOX_NR_PAGES 1
|
|
#define KVM_FFA_SPM_HANDLE_NR_PAGES 2
|
|
|
|
/*
|
|
* Maximum number of consitutents allowed in a descriptor. This number is
|
|
* arbitrary, see comment below on SG_MAX_SEGMENTS in hyp_ffa_proxy_pages().
|
|
*/
|
|
#define KVM_FFA_MAX_NR_CONSTITUENTS 4096
|
|
|
|
static inline unsigned long hyp_ffa_proxy_pages(void)
|
|
{
|
|
size_t desc_max;
|
|
unsigned long num_pages;
|
|
|
|
/*
|
|
* SG_MAX_SEGMENTS is supposed to bound the number of elements in an
|
|
* sglist, which should match the number of consituents in the
|
|
* corresponding FFA descriptor. As such, the EL2 buffer needs to be
|
|
* large enough to hold a descriptor with SG_MAX_SEGMENTS consituents
|
|
* at least. But the kernel's DMA code doesn't enforce the limit, and
|
|
* it is sometimes abused, so let's allow larger descriptors and hope
|
|
* for the best.
|
|
*/
|
|
BUILD_BUG_ON(KVM_FFA_MAX_NR_CONSTITUENTS < SG_MAX_SEGMENTS);
|
|
|
|
/*
|
|
* The hypervisor FFA proxy needs enough memory to buffer a fragmented
|
|
* descriptor returned from EL3 in response to a RETRIEVE_REQ call.
|
|
*/
|
|
desc_max = sizeof(struct ffa_mem_region) +
|
|
sizeof(struct ffa_mem_region_attributes) +
|
|
sizeof(struct ffa_composite_mem_region) +
|
|
KVM_FFA_MAX_NR_CONSTITUENTS * sizeof(struct ffa_mem_region_addr_range);
|
|
|
|
/* Plus a page each for the hypervisor's RX and TX mailboxes. */
|
|
num_pages = (2 * KVM_FFA_MBOX_NR_PAGES) + DIV_ROUND_UP(desc_max, PAGE_SIZE);
|
|
|
|
return num_pages;
|
|
}
|
|
|
|
static inline size_t pkvm_host_sve_state_size(void)
|
|
{
|
|
if (!system_supports_sve())
|
|
return 0;
|
|
|
|
return size_add(sizeof(struct cpu_sve_state),
|
|
SVE_SIG_REGS_SIZE(sve_vq_from_vl(kvm_host_sve_max_vl)));
|
|
}
|
|
|
|
int __pkvm_topup_hyp_alloc(unsigned long nr_pages);
|
|
|
|
#define kvm_call_refill_hyp_nvhe(f, ...) \
|
|
({ \
|
|
struct arm_smccc_res res; \
|
|
int __ret; \
|
|
do { \
|
|
__ret = -1; \
|
|
arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
|
|
##__VA_ARGS__, &res); \
|
|
if (WARN_ON(res.a0 != SMCCC_RET_SUCCESS)) \
|
|
break; \
|
|
\
|
|
__ret = res.a1; \
|
|
if (__ret == -ENOMEM && res.a3) { \
|
|
__ret = __pkvm_topup_hyp_alloc(res.a3); \
|
|
} else { \
|
|
break; \
|
|
} \
|
|
} while (!__ret); \
|
|
__ret; \
|
|
})
|
|
|
|
enum pkvm_ptdump_ops {
|
|
PKVM_PTDUMP_GET_LEVEL,
|
|
PKVM_PTDUMP_GET_RANGE,
|
|
PKVM_PTDUMP_WALK_RANGE,
|
|
};
|
|
|
|
struct pkvm_ptdump_log {
|
|
/* VA_BIT - PAGE_SHIFT + 1 (INVALID_PTDUMP_PFN) */
|
|
u64 pfn: 41;
|
|
bool valid: 1;
|
|
bool r: 1;
|
|
bool w: 1;
|
|
char xn: 2;
|
|
bool table: 1;
|
|
u16 page_state: 2;
|
|
u16 level: 8;
|
|
} __packed;
|
|
|
|
#define INVALID_PTDUMP_PFN (BIT(41) - 1)
|
|
|
|
struct pkvm_ptdump_log_hdr {
|
|
/* The next page */
|
|
u64 pfn_next: 48;
|
|
/* The write index in the log page */
|
|
u64 w_index: 16;
|
|
};
|
|
|
|
struct pkvm_mapping {
|
|
struct rb_node node;
|
|
u64 gfn;
|
|
u64 pfn;
|
|
u64 nr_pages;
|
|
u64 __subtree_last; /* Internal member for interval tree */
|
|
};
|
|
|
|
int pkvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm_s2_mmu *mmu,
|
|
struct kvm_pgtable_mm_ops *mm_ops, struct kvm_pgtable_pte_ops *pte_ops);
|
|
void pkvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt);
|
|
int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size, u64 phys,
|
|
enum kvm_pgtable_prot prot, void *mc,
|
|
enum kvm_pgtable_walk_flags flags);
|
|
int pkvm_pgtable_stage2_unmap(struct kvm_pgtable *pgt, u64 addr, u64 size);
|
|
int pkvm_pgtable_stage2_wrprotect(struct kvm_pgtable *pgt, u64 addr, u64 size);
|
|
int pkvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size);
|
|
bool pkvm_pgtable_stage2_test_clear_young(struct kvm_pgtable *pgt, u64 addr, u64 size, bool mkold);
|
|
int pkvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr, enum kvm_pgtable_prot prot,
|
|
enum kvm_pgtable_walk_flags flags);
|
|
kvm_pte_t pkvm_pgtable_stage2_mkyoung(struct kvm_pgtable *pgt, u64 addr,
|
|
enum kvm_pgtable_walk_flags flags);
|
|
int pkvm_pgtable_stage2_split(struct kvm_pgtable *pgt, u64 addr, u64 size, void *mc);
|
|
void pkvm_pgtable_stage2_free_unlinked(struct kvm_pgtable_mm_ops *mm_ops,
|
|
struct kvm_pgtable_pte_ops *pte_ops,
|
|
void *pgtable, s8 level);
|
|
kvm_pte_t *pkvm_pgtable_stage2_create_unlinked(struct kvm_pgtable *pgt, u64 phys, s8 level,
|
|
enum kvm_pgtable_prot prot, void *mc,
|
|
bool force_pte);
|
|
#endif /* __ARM64_KVM_PKVM_H__ */
|