947 lines
25 KiB
C
947 lines
25 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <[email protected]>
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*
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* Derived from arch/arm/include/kvm_emulate.h
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <[email protected]>
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*/
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#ifndef __ARM64_KVM_EMULATE_H__
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#define __ARM64_KVM_EMULATE_H__
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#include <linux/bitfield.h>
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#include <linux/kvm_host.h>
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#include <asm/debug-monitors.h>
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#include <asm/esr.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_nested.h>
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#include <asm/ptrace.h>
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#include <asm/cputype.h>
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#include <asm/virt.h>
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#define CURRENT_EL_SP_EL0_VECTOR 0x0
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#define CURRENT_EL_SP_ELx_VECTOR 0x200
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#define LOWER_EL_AArch64_VECTOR 0x400
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#define LOWER_EL_AArch32_VECTOR 0x600
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enum exception_type {
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except_type_sync = 0,
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except_type_irq = 0x80,
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except_type_fiq = 0x100,
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except_type_serror = 0x180,
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};
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#define kvm_exception_type_names \
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{ except_type_sync, "SYNC" }, \
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{ except_type_irq, "IRQ" }, \
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{ except_type_fiq, "FIQ" }, \
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{ except_type_serror, "SERROR" }
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bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
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void kvm_skip_instr32(struct kvm_vcpu *vcpu);
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void kvm_inject_undefined(struct kvm_vcpu *vcpu);
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void kvm_inject_vabt(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_size_fault(struct kvm_vcpu *vcpu);
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unsigned long get_except64_offset(unsigned long psr, unsigned long target_mode,
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enum exception_type type);
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unsigned long get_except64_cpsr(unsigned long old, bool has_mte,
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unsigned long sctlr, unsigned long mode);
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void kvm_vcpu_wfi(struct kvm_vcpu *vcpu);
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void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu);
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int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2);
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int kvm_inject_nested_irq(struct kvm_vcpu *vcpu);
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static inline void kvm_inject_nested_sve_trap(struct kvm_vcpu *vcpu)
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{
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u64 esr = FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SVE) |
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ESR_ELx_IL;
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kvm_inject_nested_sync(vcpu, esr);
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}
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#if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__)
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static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
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{
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return !(vcpu->arch.hcr_el2 & HCR_RW);
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}
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#else
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static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
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{
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return vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT);
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}
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#endif
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static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
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{
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if (!vcpu_has_run_once(vcpu))
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vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
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/*
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* For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C
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* get set in SCTLR_EL1 such that we can detect when the guest
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* MMU gets turned on and do the necessary cache maintenance
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* then.
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*/
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if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
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vcpu->arch.hcr_el2 |= HCR_TVM;
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}
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static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu->arch.hcr_el2;
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}
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static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 &= ~HCR_TWE;
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if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) ||
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vcpu->kvm->arch.vgic.nassgireq)
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vcpu->arch.hcr_el2 &= ~HCR_TWI;
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else
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vcpu->arch.hcr_el2 |= HCR_TWI;
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}
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static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 |= HCR_TWE;
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vcpu->arch.hcr_el2 |= HCR_TWI;
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}
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static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.vsesr_el2;
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}
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static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
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{
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vcpu->arch.vsesr_el2 = vsesr;
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}
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static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->pc;
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}
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static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate;
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}
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static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
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{
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return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
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}
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static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
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{
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if (vcpu_mode_is_32bit(vcpu))
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return kvm_condition_valid32(vcpu);
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return true;
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}
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static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
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{
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*vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
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}
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/*
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* vcpu_get_reg and vcpu_set_reg should always be passed a register number
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* coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
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* AArch32 with banked registers.
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*/
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static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
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u8 reg_num)
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{
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return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
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}
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static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
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unsigned long val)
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{
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if (reg_num != 31)
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vcpu_gp_regs(vcpu)->regs[reg_num] = val;
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}
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static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt)
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{
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switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) {
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case PSR_MODE_EL2h:
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case PSR_MODE_EL2t:
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return true;
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default:
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return false;
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}
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}
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static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu)
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{
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return vcpu_is_el2_ctxt(&vcpu->arch.ctxt);
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}
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static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt)
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{
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return (!cpus_have_final_cap(ARM64_HAS_HCR_NV1) ||
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(ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H));
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}
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static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu)
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{
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return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt);
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}
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static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt)
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{
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return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE;
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}
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static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu)
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{
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return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt);
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}
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static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt)
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{
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/*
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* We are in a hypervisor context if the vcpu mode is EL2 or
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* E2H and TGE bits are set. The latter means we are in the user space
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* of the VHE kernel. ARMv8.1 ARM describes this as 'InHost'
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*
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* Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the
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* rest of the KVM code, and will result in a misbehaving guest.
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*/
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return vcpu_is_el2_ctxt(ctxt) ||
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(__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) ||
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__vcpu_el2_tge_is_set(ctxt);
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}
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static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu)
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{
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return vcpu_has_nv(vcpu) && __is_hyp_ctxt(&vcpu->arch.ctxt);
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}
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#define PURE_EL2_SYSREG(el2) \
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case el2: { \
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*el1r = el2; \
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return true; \
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}
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#define MAPPED_EL2_SYSREG(el2, el1, fn) \
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case el2: { \
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*xlate = fn; \
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*el1r = el1; \
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return true; \
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}
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static inline bool get_el2_to_el1_mapping(unsigned int reg,
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unsigned int *el1r, u64 (**xlate)(u64))
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{
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switch (reg) {
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PURE_EL2_SYSREG( VPIDR_EL2 );
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PURE_EL2_SYSREG( VMPIDR_EL2 );
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PURE_EL2_SYSREG( ACTLR_EL2 );
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PURE_EL2_SYSREG( HCR_EL2 );
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PURE_EL2_SYSREG( MDCR_EL2 );
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PURE_EL2_SYSREG( HSTR_EL2 );
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PURE_EL2_SYSREG( HACR_EL2 );
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PURE_EL2_SYSREG( VTTBR_EL2 );
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PURE_EL2_SYSREG( VTCR_EL2 );
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PURE_EL2_SYSREG( RVBAR_EL2 );
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PURE_EL2_SYSREG( TPIDR_EL2 );
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PURE_EL2_SYSREG( HPFAR_EL2 );
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PURE_EL2_SYSREG( CNTHCTL_EL2 );
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MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1,
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translate_sctlr_el2_to_sctlr_el1 );
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MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1,
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translate_cptr_el2_to_cpacr_el1 );
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MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1,
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translate_ttbr0_el2_to_ttbr0_el1 );
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MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL );
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MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1,
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translate_tcr_el2_to_tcr_el1 );
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MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL );
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MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL );
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MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL );
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MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL );
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MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL );
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MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL );
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MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL );
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MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL );
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MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL );
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MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL );
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default:
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return false;
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}
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}
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static inline u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
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{
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u64 val = 0x8badf00d8badf00d;
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u64 (*xlate)(u64) = NULL;
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unsigned int el1r;
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if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
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goto memory_read;
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if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
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if (!is_hyp_ctxt(vcpu))
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goto memory_read;
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/*
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* If this register does not have an EL1 counterpart,
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* then read the stored EL2 version.
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*/
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if (reg == el1r)
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goto memory_read;
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/*
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* If we have a non-VHE guest and that the sysreg
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* requires translation to be used at EL1, use the
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* in-memory copy instead.
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*/
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if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
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goto memory_read;
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/* Get the current version of the EL1 counterpart. */
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WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val));
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return val;
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}
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/* EL1 register can't be on the CPU if the guest is in vEL2. */
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if (unlikely(is_hyp_ctxt(vcpu)))
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goto memory_read;
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if (__vcpu_read_sys_reg_from_cpu(reg, &val))
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return val;
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memory_read:
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return __vcpu_sys_reg(vcpu, reg);
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}
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static inline void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
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{
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u64 (*xlate)(u64) = NULL;
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unsigned int el1r;
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if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
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goto memory_write;
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if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
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if (!is_hyp_ctxt(vcpu))
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goto memory_write;
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/*
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* Always store a copy of the write to memory to avoid having
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* to reverse-translate virtual EL2 system registers for a
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* non-VHE guest hypervisor.
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*/
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__vcpu_sys_reg(vcpu, reg) = val;
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/* No EL1 counterpart? We're done here.? */
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if (reg == el1r)
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return;
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if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
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val = xlate(val);
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/* Redirect this to the EL1 version of the register. */
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WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r));
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return;
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}
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/* EL1 register can't be on the CPU if the guest is in vEL2. */
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if (unlikely(is_hyp_ctxt(vcpu)))
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goto memory_write;
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if (__vcpu_write_sys_reg_to_cpu(val, reg))
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return;
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memory_write:
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__vcpu_sys_reg(vcpu, reg) = val;
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}
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/*
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* The layout of SPSR for an AArch32 state is different when observed from an
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* AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
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* view given an AArch64 view.
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*
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* In ARM DDI 0487E.a see:
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*
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* - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426
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* - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
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* - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
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*
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* Which show the following differences:
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*
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* | Bit | AA64 | AA32 | Notes |
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* +-----+------+------+-----------------------------|
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* | 24 | DIT | J | J is RES0 in ARMv8 |
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* | 21 | SS | DIT | SS doesn't exist in AArch32 |
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*
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* ... and all other bits are (currently) common.
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*/
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static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
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{
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const unsigned long overlap = BIT(24) | BIT(21);
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unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT);
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spsr &= ~overlap;
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spsr |= dit << 21;
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return spsr;
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}
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static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
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{
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u32 mode;
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if (vcpu_mode_is_32bit(vcpu)) {
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mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
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return mode > PSR_AA32_MODE_USR;
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}
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mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
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return mode != PSR_MODE_EL0t;
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}
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static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.esr_el2;
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}
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static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
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{
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u64 esr = kvm_vcpu_get_esr(vcpu);
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if (esr & ESR_ELx_CV)
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return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
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return -1;
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}
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static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.far_el2;
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}
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static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
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{
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return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
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}
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static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.disr_el1;
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}
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|
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static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK;
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}
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|
|
static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV);
|
|
}
|
|
|
|
static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);
|
|
}
|
|
|
|
static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE);
|
|
}
|
|
|
|
static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF);
|
|
}
|
|
|
|
static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
|
|
}
|
|
|
|
static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW);
|
|
}
|
|
|
|
/* Always check for S1PTW *before* using this. */
|
|
static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR;
|
|
}
|
|
|
|
static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM);
|
|
}
|
|
|
|
static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
|
|
}
|
|
|
|
/* This one is not specific to Data Abort */
|
|
static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL);
|
|
}
|
|
|
|
static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu));
|
|
}
|
|
|
|
static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
|
|
}
|
|
|
|
static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu);
|
|
}
|
|
|
|
static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC;
|
|
}
|
|
|
|
static inline
|
|
bool kvm_vcpu_trap_is_permission_fault(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return esr_fsc_is_permission_fault(kvm_vcpu_get_esr(vcpu));
|
|
}
|
|
|
|
static inline
|
|
bool kvm_vcpu_trap_is_translation_fault(const struct kvm_vcpu *vcpu)
|
|
{
|
|
return esr_fsc_is_translation_fault(kvm_vcpu_get_esr(vcpu));
|
|
}
|
|
|
|
static inline
|
|
u64 kvm_vcpu_trap_get_perm_fault_granule(const struct kvm_vcpu *vcpu)
|
|
{
|
|
unsigned long esr = kvm_vcpu_get_esr(vcpu);
|
|
|
|
BUG_ON(!esr_fsc_is_permission_fault(esr));
|
|
return BIT(ARM64_HW_PGTABLE_LEVEL_SHIFT(esr & ESR_ELx_FSC_LEVEL));
|
|
}
|
|
|
|
static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu)
|
|
{
|
|
switch (kvm_vcpu_trap_get_fault(vcpu)) {
|
|
case ESR_ELx_FSC_EXTABT:
|
|
case ESR_ELx_FSC_SEA_TTW(-1) ... ESR_ELx_FSC_SEA_TTW(3):
|
|
case ESR_ELx_FSC_SECC:
|
|
case ESR_ELx_FSC_SECC_TTW(-1) ... ESR_ELx_FSC_SECC_TTW(3):
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
|
|
{
|
|
u64 esr = kvm_vcpu_get_esr(vcpu);
|
|
return ESR_ELx_SYS64_ISS_RT(esr);
|
|
}
|
|
|
|
static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (kvm_vcpu_abt_iss1tw(vcpu)) {
|
|
/*
|
|
* Only a permission fault on a S1PTW should be
|
|
* considered as a write. Otherwise, page tables baked
|
|
* in a read-only memslot will result in an exception
|
|
* being delivered in the guest.
|
|
*
|
|
* The drawback is that we end-up faulting twice if the
|
|
* guest is using any of HW AF/DB: a translation fault
|
|
* to map the page containing the PT (read only at
|
|
* first), then a permission fault to allow the flags
|
|
* to be set.
|
|
*/
|
|
return kvm_vcpu_trap_is_permission_fault(vcpu);
|
|
}
|
|
|
|
if (kvm_vcpu_trap_is_iabt(vcpu))
|
|
return false;
|
|
|
|
return kvm_vcpu_dabt_iswrite(vcpu);
|
|
}
|
|
|
|
static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
|
|
{
|
|
return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
|
|
}
|
|
|
|
static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (vcpu_mode_is_32bit(vcpu)) {
|
|
*vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
|
|
} else {
|
|
u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
|
|
sctlr |= SCTLR_ELx_EE;
|
|
vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
|
|
}
|
|
}
|
|
|
|
static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (vcpu_mode_is_32bit(vcpu))
|
|
return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
|
|
|
|
if (vcpu_mode_priv(vcpu))
|
|
return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE);
|
|
else
|
|
return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E);
|
|
}
|
|
|
|
static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
|
|
unsigned long data,
|
|
unsigned int len)
|
|
{
|
|
if (kvm_vcpu_is_be(vcpu)) {
|
|
switch (len) {
|
|
case 1:
|
|
return data & 0xff;
|
|
case 2:
|
|
return be16_to_cpu(data & 0xffff);
|
|
case 4:
|
|
return be32_to_cpu(data & 0xffffffff);
|
|
default:
|
|
return be64_to_cpu(data);
|
|
}
|
|
} else {
|
|
switch (len) {
|
|
case 1:
|
|
return data & 0xff;
|
|
case 2:
|
|
return le16_to_cpu(data & 0xffff);
|
|
case 4:
|
|
return le32_to_cpu(data & 0xffffffff);
|
|
default:
|
|
return le64_to_cpu(data);
|
|
}
|
|
}
|
|
|
|
return data; /* Leave LE untouched */
|
|
}
|
|
|
|
static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
|
|
unsigned long data,
|
|
unsigned int len)
|
|
{
|
|
if (kvm_vcpu_is_be(vcpu)) {
|
|
switch (len) {
|
|
case 1:
|
|
return data & 0xff;
|
|
case 2:
|
|
return cpu_to_be16(data & 0xffff);
|
|
case 4:
|
|
return cpu_to_be32(data & 0xffffffff);
|
|
default:
|
|
return cpu_to_be64(data);
|
|
}
|
|
} else {
|
|
switch (len) {
|
|
case 1:
|
|
return data & 0xff;
|
|
case 2:
|
|
return cpu_to_le16(data & 0xffff);
|
|
case 4:
|
|
return cpu_to_le32(data & 0xffffffff);
|
|
default:
|
|
return cpu_to_le64(data);
|
|
}
|
|
}
|
|
|
|
return data; /* Leave LE untouched */
|
|
}
|
|
|
|
static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu)
|
|
{
|
|
WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION));
|
|
vcpu_set_flag(vcpu, INCREMENT_PC);
|
|
}
|
|
|
|
#define kvm_pend_exception(v, e) \
|
|
do { \
|
|
WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \
|
|
vcpu_set_flag((v), PENDING_EXCEPTION); \
|
|
vcpu_set_flag((v), e); \
|
|
} while (0)
|
|
|
|
#define __build_check_all_or_none(r, bits) \
|
|
BUILD_BUG_ON(((r) & (bits)) && ((r) & (bits)) != (bits))
|
|
|
|
#define __cpacr_to_cptr_clr(clr, set) \
|
|
({ \
|
|
u64 cptr = 0; \
|
|
\
|
|
if ((set) & CPACR_ELx_FPEN) \
|
|
cptr |= CPTR_EL2_TFP; \
|
|
if ((set) & CPACR_ELx_ZEN) \
|
|
cptr |= CPTR_EL2_TZ; \
|
|
if ((set) & CPACR_ELx_SMEN) \
|
|
cptr |= CPTR_EL2_TSM; \
|
|
if ((clr) & CPACR_ELx_TTA) \
|
|
cptr |= CPTR_EL2_TTA; \
|
|
if ((clr) & CPTR_EL2_TAM) \
|
|
cptr |= CPTR_EL2_TAM; \
|
|
if ((clr) & CPTR_EL2_TCPAC) \
|
|
cptr |= CPTR_EL2_TCPAC; \
|
|
\
|
|
cptr; \
|
|
})
|
|
|
|
#define __cpacr_to_cptr_set(clr, set) \
|
|
({ \
|
|
u64 cptr = 0; \
|
|
\
|
|
if ((clr) & CPACR_ELx_FPEN) \
|
|
cptr |= CPTR_EL2_TFP; \
|
|
if ((clr) & CPACR_ELx_ZEN) \
|
|
cptr |= CPTR_EL2_TZ; \
|
|
if ((clr) & CPACR_ELx_SMEN) \
|
|
cptr |= CPTR_EL2_TSM; \
|
|
if ((set) & CPACR_ELx_TTA) \
|
|
cptr |= CPTR_EL2_TTA; \
|
|
if ((set) & CPTR_EL2_TAM) \
|
|
cptr |= CPTR_EL2_TAM; \
|
|
if ((set) & CPTR_EL2_TCPAC) \
|
|
cptr |= CPTR_EL2_TCPAC; \
|
|
\
|
|
cptr; \
|
|
})
|
|
|
|
#define cpacr_clear_set(clr, set) \
|
|
do { \
|
|
BUILD_BUG_ON((set) & CPTR_VHE_EL2_RES0); \
|
|
BUILD_BUG_ON((clr) & CPACR_ELx_E0POE); \
|
|
__build_check_all_or_none((clr), CPACR_ELx_FPEN); \
|
|
__build_check_all_or_none((set), CPACR_ELx_FPEN); \
|
|
__build_check_all_or_none((clr), CPACR_ELx_ZEN); \
|
|
__build_check_all_or_none((set), CPACR_ELx_ZEN); \
|
|
__build_check_all_or_none((clr), CPACR_ELx_SMEN); \
|
|
__build_check_all_or_none((set), CPACR_ELx_SMEN); \
|
|
\
|
|
if (has_vhe() || has_hvhe()) \
|
|
sysreg_clear_set(cpacr_el1, clr, set); \
|
|
else \
|
|
sysreg_clear_set(cptr_el2, \
|
|
__cpacr_to_cptr_clr(clr, set), \
|
|
__cpacr_to_cptr_set(clr, set));\
|
|
} while (0)
|
|
|
|
static __always_inline void kvm_write_cptr_el2(u64 val)
|
|
{
|
|
if (has_vhe() || has_hvhe())
|
|
write_sysreg(val, cpacr_el1);
|
|
else
|
|
write_sysreg(val, cptr_el2);
|
|
}
|
|
|
|
/* Resets the value of cptr_el2 when returning to the host. */
|
|
static __always_inline void __kvm_reset_cptr_el2(struct kvm *kvm)
|
|
{
|
|
u64 val;
|
|
|
|
if (has_vhe()) {
|
|
val = (CPACR_ELx_FPEN | CPACR_EL1_ZEN_EL1EN);
|
|
if (cpus_have_final_cap(ARM64_SME))
|
|
val |= CPACR_EL1_SMEN_EL1EN;
|
|
} else if (has_hvhe()) {
|
|
val = CPACR_ELx_FPEN;
|
|
|
|
if (!kvm_has_sve(kvm) || !guest_owns_fp_regs())
|
|
val |= CPACR_ELx_ZEN;
|
|
if (cpus_have_final_cap(ARM64_SME))
|
|
val |= CPACR_ELx_SMEN;
|
|
} else {
|
|
val = CPTR_NVHE_EL2_RES1;
|
|
|
|
if (kvm_has_sve(kvm) && guest_owns_fp_regs())
|
|
val |= CPTR_EL2_TZ;
|
|
if (!cpus_have_final_cap(ARM64_SME))
|
|
val |= CPTR_EL2_TSM;
|
|
}
|
|
|
|
kvm_write_cptr_el2(val);
|
|
}
|
|
|
|
static inline void kvm_calculate_fgu_traps(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm *kvm = vcpu->kvm;
|
|
|
|
if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags))
|
|
return;
|
|
|
|
kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 |
|
|
HFGxTR_EL2_nMAIR2_EL1 |
|
|
HFGxTR_EL2_nS2POR_EL1 |
|
|
HFGxTR_EL2_nACCDATA_EL1 |
|
|
HFGxTR_EL2_nSMPRI_EL1_MASK |
|
|
HFGxTR_EL2_nTPIDR2_EL0_MASK);
|
|
|
|
if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
|
|
kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS|
|
|
HFGITR_EL2_TLBIRVALE1OS |
|
|
HFGITR_EL2_TLBIRVAAE1OS |
|
|
HFGITR_EL2_TLBIRVAE1OS |
|
|
HFGITR_EL2_TLBIVAALE1OS |
|
|
HFGITR_EL2_TLBIVALE1OS |
|
|
HFGITR_EL2_TLBIVAAE1OS |
|
|
HFGITR_EL2_TLBIASIDE1OS |
|
|
HFGITR_EL2_TLBIVAE1OS |
|
|
HFGITR_EL2_TLBIVMALLE1OS);
|
|
|
|
if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
|
|
kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 |
|
|
HFGITR_EL2_TLBIRVALE1 |
|
|
HFGITR_EL2_TLBIRVAAE1 |
|
|
HFGITR_EL2_TLBIRVAE1 |
|
|
HFGITR_EL2_TLBIRVAALE1IS|
|
|
HFGITR_EL2_TLBIRVALE1IS |
|
|
HFGITR_EL2_TLBIRVAAE1IS |
|
|
HFGITR_EL2_TLBIRVAE1IS |
|
|
HFGITR_EL2_TLBIRVAALE1OS|
|
|
HFGITR_EL2_TLBIRVALE1OS |
|
|
HFGITR_EL2_TLBIRVAAE1OS |
|
|
HFGITR_EL2_TLBIRVAE1OS);
|
|
|
|
if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP))
|
|
kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A;
|
|
|
|
if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2))
|
|
kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP |
|
|
HFGITR_EL2_ATS1E1WP);
|
|
|
|
if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP))
|
|
kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 |
|
|
HFGxTR_EL2_nPIR_EL1);
|
|
|
|
if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP))
|
|
kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 |
|
|
HFGxTR_EL2_nPOR_EL0);
|
|
|
|
if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP))
|
|
kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 |
|
|
HAFGRTR_EL2_RES1);
|
|
|
|
set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags);
|
|
}
|
|
|
|
#ifdef __KVM_NVHE_HYPERVISOR__
|
|
#define kvm_reset_cptr_el2(v) __kvm_reset_cptr_el2(kern_hyp_va((v)->kvm))
|
|
#else
|
|
#define kvm_reset_cptr_el2(v) __kvm_reset_cptr_el2((v)->kvm)
|
|
#endif
|
|
|
|
/*
|
|
* Returns a 'sanitised' view of CPTR_EL2, translating from nVHE to the VHE
|
|
* format if E2H isn't set.
|
|
*/
|
|
static inline u64 vcpu_sanitised_cptr_el2(const struct kvm_vcpu *vcpu)
|
|
{
|
|
u64 cptr = __vcpu_sys_reg(vcpu, CPTR_EL2);
|
|
|
|
if (!vcpu_el2_e2h_is_set(vcpu))
|
|
cptr = translate_cptr_el2_to_cpacr_el1(cptr);
|
|
|
|
return cptr;
|
|
}
|
|
|
|
static inline bool ____cptr_xen_trap_enabled(const struct kvm_vcpu *vcpu,
|
|
unsigned int xen)
|
|
{
|
|
switch (xen) {
|
|
case 0b00:
|
|
case 0b10:
|
|
return true;
|
|
case 0b01:
|
|
return vcpu_el2_tge_is_set(vcpu) && !vcpu_is_el2(vcpu);
|
|
case 0b11:
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
#define __guest_hyp_cptr_xen_trap_enabled(vcpu, xen) \
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(!vcpu_has_nv(vcpu) ? false : \
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____cptr_xen_trap_enabled(vcpu, \
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SYS_FIELD_GET(CPACR_ELx, xen, \
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vcpu_sanitised_cptr_el2(vcpu))))
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static inline bool guest_hyp_fpsimd_traps_enabled(const struct kvm_vcpu *vcpu)
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{
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return __guest_hyp_cptr_xen_trap_enabled(vcpu, FPEN);
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}
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static inline bool guest_hyp_sve_traps_enabled(const struct kvm_vcpu *vcpu)
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{
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return __guest_hyp_cptr_xen_trap_enabled(vcpu, ZEN);
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}
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/* Reset a vcpu's core registers. */
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static inline void kvm_reset_vcpu_core(struct kvm_vcpu *vcpu)
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{
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u32 pstate;
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|
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if (vcpu_el1_is_32bit(vcpu)) {
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pstate = VCPU_RESET_PSTATE_SVC;
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} else if (vcpu_has_nv(vcpu)) {
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pstate = VCPU_RESET_PSTATE_EL2;
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} else {
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pstate = VCPU_RESET_PSTATE_EL1;
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}
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/* Reset core registers */
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memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu)));
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memset(&vcpu->arch.ctxt.fp_regs, 0, sizeof(vcpu->arch.ctxt.fp_regs));
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vcpu->arch.ctxt.spsr_abt = 0;
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vcpu->arch.ctxt.spsr_und = 0;
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vcpu->arch.ctxt.spsr_irq = 0;
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vcpu->arch.ctxt.spsr_fiq = 0;
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vcpu_gp_regs(vcpu)->pstate = pstate;
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}
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|
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/* PSCI reset handling for a vcpu. */
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|
static inline void kvm_reset_vcpu_psci(struct kvm_vcpu *vcpu,
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|
struct vcpu_reset_state *reset_state)
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|
{
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|
unsigned long target_pc = reset_state->pc;
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|
|
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/* Gracefully handle Thumb2 entry point */
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if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
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target_pc &= ~1UL;
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vcpu_set_thumb(vcpu);
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}
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|
|
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/* Propagate caller endianness */
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|
if (reset_state->be)
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kvm_vcpu_set_be(vcpu);
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|
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*vcpu_pc(vcpu) = target_pc;
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vcpu_set_reg(vcpu, 0, reset_state->r0);
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|
}
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|
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#endif /* __ARM64_KVM_EMULATE_H__ */
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