556 lines
14 KiB
C
556 lines
14 KiB
C
/*
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* Copyright (c) 202X Amlogic, Inc. All rights reserved.
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*
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* This source code is subject to the terms and conditions defined in the
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* file 'LICENSE' which is part of this source code package.
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*
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* Description:
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*/
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#ifndef CHIP_INTF_REG_H
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#define CHIP_INTF_REG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CHIP_INTF_REG_BASE (0xf00000)
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#define RG_AON_A0 (CHIP_INTF_REG_BASE + 0x0)
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// Bit 31 :0 rg_pin_mux0 U RW default = 'h0
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typedef union RG_AON_A0_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pin_mux0 : 32;
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} b;
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} RG_AON_A0_FIELD_T;
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#define RG_AON_A1 (CHIP_INTF_REG_BASE + 0x4)
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// Bit 31 :0 rg_pin_mux1 U RW default = 'hffbf0f0
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typedef union RG_AON_A1_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pin_mux1 : 32;
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} b;
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} RG_AON_A1_FIELD_T;
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#define RG_AON_A2 (CHIP_INTF_REG_BASE + 0x8)
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// Bit 31 :0 rg_pin_mux2 U RW default = 'h40f0f
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typedef union RG_AON_A2_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pin_mux2 : 32;
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} b;
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} RG_AON_A2_FIELD_T;
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#define RG_AON_A3 (CHIP_INTF_REG_BASE + 0xc)
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// Bit 31 :0 rg_pin_mux3 U RW default = 'h0
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typedef union RG_AON_A3_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pin_mux3 : 32;
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} b;
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} RG_AON_A3_FIELD_T;
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#define RG_AON_A4 (CHIP_INTF_REG_BASE + 0x10)
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// Bit 31 :0 rg_pin_mux4 U RW default = 'h0
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typedef union RG_AON_A4_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pin_mux4 : 32;
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} b;
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} RG_AON_A4_FIELD_T;
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#define RG_AON_A5 (CHIP_INTF_REG_BASE + 0x14)
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// Bit 31 :0 rg_pin_mux5 U RW default = 'h0
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typedef union RG_AON_A5_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pin_mux5 : 32;
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} b;
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} RG_AON_A5_FIELD_T;
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#define RG_AON_A6 (CHIP_INTF_REG_BASE + 0x18)
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// Bit 31 :0 rg_pin_mux6 U RW default = 'h0
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typedef union RG_AON_A6_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pin_mux6 : 32;
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} b;
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} RG_AON_A6_FIELD_T;
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#define RG_AON_A7 (CHIP_INTF_REG_BASE + 0x1c)
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// Bit 31 :0 rg_pin_mux7 U RW default = 'h0
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typedef union RG_AON_A7_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pin_mux7 : 32;
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} b;
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} RG_AON_A7_FIELD_T;
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#define RG_AON_A8 (CHIP_INTF_REG_BASE + 0x20)
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// Bit 0 rg_test_n_gpio_en_n U RW default = 'h0
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typedef union RG_AON_A8_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_test_n_gpio_en_n : 1;
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unsigned int rsvd_0 : 31;
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} b;
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} RG_AON_A8_FIELD_T;
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#define RG_AON_A9 (CHIP_INTF_REG_BASE + 0x24)
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// Bit 18 :0 rg_pad_gpioa_pull_up U RW default = 'h18000
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typedef union RG_AON_A9_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pad_gpioA_pull_up : 19;
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unsigned int rsvd_0 : 13;
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} b;
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} RG_AON_A9_FIELD_T;
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#define RG_AON_A10 (CHIP_INTF_REG_BASE + 0x28)
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// Bit 18 :0 rg_pad_gpioa_o U RW default = 'h7ffff
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typedef union RG_AON_A10_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pad_gpioA_o : 19;
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unsigned int rsvd_0 : 13;
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} b;
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} RG_AON_A10_FIELD_T;
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#define RG_AON_A11 (CHIP_INTF_REG_BASE + 0x2c)
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// Bit 18 :0 rg_pad_gpioa_en_n U RW default = 'h7ffff
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typedef union RG_AON_A11_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pad_gpioA_en_n : 19;
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unsigned int rsvd_0 : 13;
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} b;
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} RG_AON_A11_FIELD_T;
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#define RG_AON_A12 (CHIP_INTF_REG_BASE + 0x30)
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// Bit 18 :0 ro_pad_gpioa_i U RO default = 'h0
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typedef union RG_AON_A12_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_pad_gpioA_i : 19;
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unsigned int rsvd_0 : 13;
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} b;
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} RG_AON_A12_FIELD_T;
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#define RG_AON_A13 (CHIP_INTF_REG_BASE + 0x34)
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// Bit 18 :0 ro_pad_gpioa_pull_up U RO default = 'h0
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typedef union RG_AON_A13_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_pad_gpioA_pull_up : 19;
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unsigned int rsvd_0 : 13;
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} b;
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} RG_AON_A13_FIELD_T;
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#define RG_AON_A14 (CHIP_INTF_REG_BASE + 0x38)
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// Bit 31 :0 rg_prod_tst_cfg0 U RW default = 'h24
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typedef union RG_AON_A14_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_prod_tst_cfg0 : 32;
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} b;
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} RG_AON_A14_FIELD_T;
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#define RG_AON_A15 (CHIP_INTF_REG_BASE + 0x3c)
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// Bit 31 :0 rg_prod_tst_cfg1 U RW default = 'h0
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typedef union RG_AON_A15_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_prod_tst_cfg1 : 32;
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} b;
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} RG_AON_A15_FIELD_T;
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#define RG_AON_A16 (CHIP_INTF_REG_BASE + 0x40)
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// Bit 31 :0 rg_wf_debug0 U RW default = 'h0
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typedef union RG_AON_A16_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_wf_debug0 : 32;
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} b;
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} RG_AON_A16_FIELD_T;
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#define RG_AON_A17 (CHIP_INTF_REG_BASE + 0x44)
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// Bit 31 :0 rg_wf_debug1 U RW default = 'h0
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typedef union RG_AON_A17_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_wf_debug1 : 32;
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} b;
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} RG_AON_A17_FIELD_T;
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#define RG_AON_A18 (CHIP_INTF_REG_BASE + 0x48)
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// Bit 31 :0 rg_mac_timer_cfg1 U RW default = 'h10a00
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typedef union RG_AON_A18_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_mac_timer_cfg1 : 32;
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} b;
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} RG_AON_A18_FIELD_T;
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#define RG_AON_A19 (CHIP_INTF_REG_BASE + 0x4c)
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// Bit 31 :0 rg_mac_time_low U RW default = 'h0
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typedef union RG_AON_A19_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_mac_time_low : 32;
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} b;
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} RG_AON_A19_FIELD_T;
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#define RG_AON_A20 (CHIP_INTF_REG_BASE + 0x50)
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// Bit 31 :0 rg_mac_time_high U RW default = 'h0
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typedef union RG_AON_A20_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_mac_time_high : 32;
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} b;
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} RG_AON_A20_FIELD_T;
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#define RG_AON_A21 (CHIP_INTF_REG_BASE + 0x54)
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// Bit 31 :0 rg_tsf_clk_cfg U RW default = 'h9
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typedef union RG_AON_A21_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_tsf_clk_cfg : 32;
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} b;
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} RG_AON_A21_FIELD_T;
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#define RG_AON_A22 (CHIP_INTF_REG_BASE + 0x58)
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// Bit 31 :0 ro_prod_tst_sts0 U RO default = 'h0
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typedef union RG_AON_A22_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_prod_tst_sts0 : 32;
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} b;
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} RG_AON_A22_FIELD_T;
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#define RG_AON_A23 (CHIP_INTF_REG_BASE + 0x5c)
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// Bit 31 :0 ro_prod_tst_sts1 U RO default = 'h0
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typedef union RG_AON_A23_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_prod_tst_sts1 : 32;
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} b;
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} RG_AON_A23_FIELD_T;
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#define RG_AON_A24 (CHIP_INTF_REG_BASE + 0x60)
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// Bit 31 :0 rg_wf_debug2 U RW default = 'h0
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typedef union RG_AON_A24_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_wf_debug2 : 32;
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} b;
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} RG_AON_A24_FIELD_T;
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#define RG_AON_A25 (CHIP_INTF_REG_BASE + 0x64)
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// Bit 31 :0 rg_wf_debug3 U RW default = 'h0
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typedef union RG_AON_A25_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_wf_debug3 : 32;
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} b;
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} RG_AON_A25_FIELD_T;
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#define RG_AON_A29 (CHIP_INTF_REG_BASE + 0x74)
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// Bit 31 :0 rg_ana_bpll_cfg U RW default = 'h0
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typedef union RG_AON_A29_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_ana_bpll_cfg : 32;
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} b;
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} RG_AON_A29_FIELD_T;
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#define RG_AON_A30 (CHIP_INTF_REG_BASE + 0x78)
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// Bit 31 :0 rg_always_on_cfg4 U RW default = 'hc1b0
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typedef union RG_AON_A30_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_always_on_cfg4 : 32;
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} b;
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} RG_AON_A30_FIELD_T;
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#define RG_AON_A31 (CHIP_INTF_REG_BASE + 0x7c)
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// Bit 31 :0 rg_always_on_cfg5 U RW default = 'hc1b0
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typedef union RG_AON_A31_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_always_on_cfg5 : 32;
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} b;
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} RG_AON_A31_FIELD_T;
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#define RG_AON_A32 (CHIP_INTF_REG_BASE + 0x80)
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// Bit 31 :0 rg_mac_timer_cfg2 U RW default = 'h7d0001
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typedef union RG_AON_A32_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_mac_timer_cfg2 : 32;
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} b;
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} RG_AON_A32_FIELD_T;
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#define RG_AON_A33 (CHIP_INTF_REG_BASE + 0x84)
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// Bit 31 :0 rg_mac_timer_cfg3 U RW default = 'h800100
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typedef union RG_AON_A33_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_mac_timer_cfg3 : 32;
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} b;
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} RG_AON_A33_FIELD_T;
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#define RG_AON_A34 (CHIP_INTF_REG_BASE + 0x88)
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// Bit 31 :0 ro_always_on_sts1 U RO default = 'h0
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typedef union RG_AON_A34_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_always_on_sts1 : 32;
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} b;
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} RG_AON_A34_FIELD_T;
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#define RG_AON_A35 (CHIP_INTF_REG_BASE + 0x8c)
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// Bit 31 :0 ro_always_on_sts2 U RO default = 'h0
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typedef union RG_AON_A35_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_always_on_sts2 : 32;
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} b;
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} RG_AON_A35_FIELD_T;
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#define RG_AON_A36 (CHIP_INTF_REG_BASE + 0x90)
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// Bit 31 :0 ro_always_on_sts3 U RO default = 'h0
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typedef union RG_AON_A36_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_always_on_sts3 : 32;
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} b;
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} RG_AON_A36_FIELD_T;
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#define RG_AON_A37 (CHIP_INTF_REG_BASE + 0x94)
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// Bit 31 :0 rg_intf_rsvd0 U RW default = 'h0
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typedef union RG_AON_A37_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_intf_rsvd0 : 32;
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} b;
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} RG_AON_A37_FIELD_T;
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#define RG_AON_A38 (CHIP_INTF_REG_BASE + 0x98)
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// Bit 31 :0 rg_pmu_power_dur_thr U RW default = 'h0
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typedef union RG_AON_A38_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pmu_power_dur_thr : 32;
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} b;
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} RG_AON_A38_FIELD_T;
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#define RG_AON_A39 (CHIP_INTF_REG_BASE + 0x9c)
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// Bit 31 :0 rg_gated_ctrl U RW default = 'h2
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typedef union RG_AON_A39_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_gated_ctrl : 32;
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} b;
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} RG_AON_A39_FIELD_T;
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#define RG_AON_A40 (CHIP_INTF_REG_BASE + 0xa0)
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// Bit 7 :0 rg_dig_timebase U RW default = 'h28
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typedef union RG_AON_A40_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_dig_timebase : 8;
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unsigned int rsvd_0 : 24;
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} b;
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} RG_AON_A40_FIELD_T;
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#define RG_AON_A41 (CHIP_INTF_REG_BASE + 0xa4)
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// Bit 31 :0 ro_metal_rev U RO default = 'h0
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typedef union RG_AON_A41_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_metal_rev : 32;
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} b;
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} RG_AON_A41_FIELD_T;
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#define RG_AON_A42 (CHIP_INTF_REG_BASE + 0xa8)
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// Bit 31 :0 rg_pmu_clk_cfg U RW default = 'h113
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typedef union RG_AON_A42_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int rg_pmu_clk_cfg : 32;
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} b;
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} RG_AON_A42_FIELD_T;
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#define RG_AON_A44 (CHIP_INTF_REG_BASE + 0xb0)
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// Bit 31 :0 ro_efuse_rd0 U RO default = 'h0
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typedef union RG_AON_A44_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_efuse_rd0 : 32;
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} b;
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} RG_AON_A44_FIELD_T;
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#define RG_AON_A45 (CHIP_INTF_REG_BASE + 0xb4)
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// Bit 31 :0 ro_efuse_rd1 U RO default = 'h0
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typedef union RG_AON_A45_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_efuse_rd1 : 32;
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} b;
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} RG_AON_A45_FIELD_T;
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#define RG_AON_A46 (CHIP_INTF_REG_BASE + 0xb8)
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// Bit 31 :0 ro_efuse_rd2 U RO default = 'h0
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typedef union RG_AON_A46_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_efuse_rd2 : 32;
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} b;
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} RG_AON_A46_FIELD_T;
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#define RG_AON_A47 (CHIP_INTF_REG_BASE + 0xbc)
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// Bit 31 :0 ro_efuse_rd3 U RO default = 'h0
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typedef union RG_AON_A47_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_efuse_rd3 : 32;
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} b;
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} RG_AON_A47_FIELD_T;
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#define RG_AON_A48 (CHIP_INTF_REG_BASE + 0xc0)
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// Bit 31 :0 ro_efuse_rd4 U RO default = 'h0
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typedef union RG_AON_A48_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_efuse_rd4 : 32;
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} b;
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} RG_AON_A48_FIELD_T;
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#define RG_AON_A49 (CHIP_INTF_REG_BASE + 0xc4)
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// Bit 31 :0 ro_efuse_rd5 U RO default = 'h0
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typedef union RG_AON_A49_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_efuse_rd5 : 32;
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} b;
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} RG_AON_A49_FIELD_T;
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#define RG_AON_A50 (CHIP_INTF_REG_BASE + 0xc8)
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// Bit 31 :0 ro_efuse_rd6 U RO default = 'h0
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typedef union RG_AON_A50_FIELD
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{
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unsigned int data;
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struct
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{
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unsigned int ro_efuse_rd6 : 32;
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} b;
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} RG_AON_A50_FIELD_T;
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#define RG_AON_A51 (CHIP_INTF_REG_BASE + 0xcc)
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// Bit 31 :0 ro_efuse_rd7 U RO default = 'h0
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typedef union RG_AON_A51_FIELD
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{
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unsigned int data;
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struct
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|
{
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unsigned int ro_efuse_rd7 : 32;
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} b;
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} RG_AON_A51_FIELD_T;
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#endif /* CHIP_INTF_REG_H */
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