1259 lines
38 KiB
C
1259 lines
38 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
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/*
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* Copyright (C) 2025 Amlogic, Inc. All rights reserved
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <linux/version.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-common.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-mc.h>
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#include <media/v4l2-subdev.h>
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/* C4 CSI-2 submodule definition */
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enum {
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SUBMD_APHY,
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SUBMD_DPHY,
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SUBMD_HOST,
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};
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#define CSI_SUBMD_MASK GENMASK(17, 16)
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#define CSI_SUBMD_SHIFT 16
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#define CSI_SUBMD(x) (((x) & (CSI_SUBMD_MASK)) >> (CSI_SUBMD_SHIFT))
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#define CSI_REG_ADDR_MASK GENMASK(15, 0)
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#define CSI_REG_ADDR(x) ((x) & (CSI_REG_ADDR_MASK))
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#define CSI_REG_A(x) ((SUBMD_APHY << CSI_SUBMD_SHIFT) | (x))
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#define CSI_REG_D(x) ((SUBMD_DPHY << CSI_SUBMD_SHIFT) | (x))
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#define CSI_REG_H(x) ((SUBMD_HOST << CSI_SUBMD_SHIFT) | (x))
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#define C4_CSI_CLOCK_NUM_MAX 3
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#define C4_CSI_SUBDEV_NAME "c4-csi"
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#define MIPI_PROC_DPHY_CTRL0 CSI_REG_A(0x44)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_C_CTRL_MASK GENMASK(3, 0)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_C_CTRL(x) ((x) << 0)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_R_CTRL_MASK GENMASK(7, 4)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_R_CTRL(x) ((x) << 4)
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#define MIPI_PROC_DPHY_CTRL0_HS_D2S_CUR_CTRL_MASK GENMASK(9, 8)
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#define MIPI_PROC_DPHY_CTRL0_HS_D2S_CUR_CTRL(x) ((x) << 8)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_RHALF_EN_MASK BIT(10)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_RHALF_EN(x) ((x) << 10)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_MAINMAX_MASK BIT(11)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_MAINMAX(x) ((x) << 11)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_PATA_CUR_CTRL_MASK GENMASK(14, 12)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_PATA_CUR_CTRL(x) ((x) << 12)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_ZATA_CUR_CTRL_MASK GENMASK(18, 16)
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#define MIPI_PROC_DPHY_CTRL0_HS_EQ_ZATA_CUR_CTRL(x) ((x) << 16)
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#define MIPI_PROC_DPHY_CTRL0_LP_COMP_CUR_CTRL_MASK GENMASK(21, 20)
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#define MIPI_PROC_DPHY_CTRL0_LP_COMP_CUR_CTRL(x) ((x) << 20)
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#define MIPI_PROC_DPHY_CTRL0_LP_VTH_CTRL_MASK GENMASK(25, 22)
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#define MIPI_PROC_DPHY_CTRL0_LP_VTH_CTRL(x) ((x) << 22)
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#define MIPI_PROC_DPHY_CTRL0_LP_VTL_CTRL_MASK GENMASK(29, 26)
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#define MIPI_PROC_DPHY_CTRL0_LP_VTL_CTRL(x) ((x) << 26)
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#define MIPI_PROC_DPHY_CTRL0_CSI_TOP_EN_MASK BIT(31)
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#define MIPI_PROC_DPHY_CTRL0_CSI_TOP_EN BIT(31)
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#define MIPI_PROC_DPHY_CTRL0_CSI_TOP_DIS (0 << 31)
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#define MIPI_PROC_DPHY_CTRL1 CSI_REG_A(0x48)
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#define MIPI_PROC_DPHY_CTRL1_RTERN_TRIMED_VAL_MASK GENMASK(3, 0)
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#define MIPI_PROC_DPHY_CTRL1_RTERN_TRIMED_VAL(x) ((x) << 0)
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#define MIPI_PROC_DPHY_CTRL2 CSI_REG_A(0x4c)
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#define MIPI_PROC_DPHY_CTRL2_LANE3_CLK_SRC_SEL_MASK BIT(6)
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#define MIPI_PROC_DPHY_CTRL2_LANE3_CLK_SRC_SEL(x) ((x) << 6)
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#define MIPI_PROC_DPHY_CTRL2_LANE4_CLK_SRC_SEL_MASK BIT(7)
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#define MIPI_PROC_DPHY_CTRL2_LANE4_CLK_SRC_SEL(x) ((x) << 7)
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#define MIPI_PROC_DPHY_CTRL3 CSI_REG_A(0x50)
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#define MIPI_PROC_DPHY_CTRL3_CH0_SEL_DPHY_MASK BIT(20)
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#define MIPI_PROC_DPHY_CTRL3_CH0_SEL_DPHY(x) ((x) << 20)
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#define MIPI_PROC_DPHY_CTRL3_CH1_SEL_DPHY_MASK BIT(21)
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#define MIPI_PROC_DPHY_CTRL3_CH1_SEL_DPHY(x) ((x) << 21)
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#define MIPI_PROC_DPHY_CTRL3_CH2_SEL_DPHY_MASK BIT(22)
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#define MIPI_PROC_DPHY_CTRL3_CH2_SEL_DPHY(x) ((x) << 22)
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#define MIPI_PROC_DPHY_CTRL3_CH3_SEL_DPHY_MASK BIT(23)
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#define MIPI_PROC_DPHY_CTRL3_CH3_SEL_DPHY(x) ((x) << 23)
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#define MIPI_PROC_DPHY_CTRL3_CH4_SEL_DPHY_MASK BIT(24)
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#define MIPI_PROC_DPHY_CTRL3_CH4_SEL_DPHY(x) ((x) << 24)
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#define MIPI_PROC_DPHY_CTRL3_CH5_SEL_DPHY_MASK BIT(25)
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#define MIPI_PROC_DPHY_CTRL3_CH5_SEL_DPHY(x) ((x) << 25)
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#define MIPI_PROC_DPHY_CTRL3_SKEW_FROM_DPHY_MASK BIT(26)
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#define MIPI_PROC_DPHY_CTRL3_SKEW_FROM_DPHY_EN BIT(26)
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#define MIPI_PROC_DPHY_CTRL3_SKEW_FROM_DPHY_DIS (0 << 26)
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/* C4 MIPI DPHY registers */
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#define MIPI_PHY_CTRL CSI_REG_D(0x00)
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#define MIPI_PHY_CTRL_DATA_LANE0_EN (0 << 0)
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#define MIPI_PHY_CTRL_DATA_LANE0_DIS BIT(0)
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#define MIPI_PHY_CTRL_DATA_LANE1_EN (0 << 1)
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#define MIPI_PHY_CTRL_DATA_LANE1_DIS BIT(1)
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#define MIPI_PHY_CTRL_DATA_LANE2_EN (0 << 2)
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#define MIPI_PHY_CTRL_DATA_LANE2_DIS BIT(2)
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#define MIPI_PHY_CTRL_DATA_LANE3_EN (0 << 3)
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#define MIPI_PHY_CTRL_DATA_LANE3_DIS BIT(3)
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#define MIPI_PHY_CTRL_CLOCK_LANE_EN (0 << 4)
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#define MIPI_PHY_CTRL_CLOCK_LANE_DIS BIT(4)
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#define MIPI_PHY_CTRL_SOFT_RESET_MASK BIT(31)
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#define MIPI_PHY_CTRL_SOFT_RESET_ACTIVE BIT(31)
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#define MIPI_PHY_CTRL_SOFT_RESET_EXIT (0 << 31)
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#define MIPI_PHY_CLK_LANE_CTRL CSI_REG_D(0x04)
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#define MIPI_PHY_CLK_LANE_CTRL_FORCE_ULPS_ENTER BIT(0)
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#define MIPI_PHY_CLK_LANE_CTRL_FORCE_ULPS_EXIT BIT(1)
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#define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS (0 << 3)
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#define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS_2 BIT(3)
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#define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS_4 (2 << 3)
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#define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS_8 (3 << 3)
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#define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS_16 (4 << 3)
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#define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_EN BIT(6)
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#define MIPI_PHY_CLK_LANE_CTRL_LPEN_DIS BIT(7)
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#define MIPI_PHY_CLK_LANE_CTRL_END_EN BIT(8)
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#define MIPI_PHY_CLK_LANE_CTRL_HS_RX_EN BIT(9)
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#define MIPI_PHY_CLK_LANE_CTRL_FORCE_LP_EN BIT(10)
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#define MIPI_PHY_CLK_LANE_CTRL_FORCH_TH_EN BIT(11)
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#define MIPI_PHY_CLK_LANE_CTRL_ALIGN_RD_DLY_MASK GENMASK(14, 12)
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#define MIPI_PHY_CLK_LANE_CTRL_ALIGN_RD_DLY_4 (4 << 12)
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#define MIPI_PHY_CLK_LANE_CTRL_ALIGN_EN_MASK BIT(16)
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#define MIPI_PHY_CLK_LANE_CTRL_ALIGN_EN BIT(16)
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#define MIPI_PHY_CLK_LANE_CTRL_ALIGN_DIS (0 << 16)
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#define MIPI_PHY_DATA_LANE_CTRL1 CSI_REG_D(0x0c)
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#define MIPI_PHY_DATA_LANE_CTRL1_INSERT_ERRESC BIT(0)
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#define MIPI_PHY_DATA_LANE_CTRL1_HS_SYNC_CHK_EN BIT(1)
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#define MIPI_PHY_DATA_LANE_CTRL1_HS_SYNC_CHK_DIS (0 << 1)
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#define MIPI_PHY_DATA_LANE_CTRL1_PIPE_MASK GENMASK(6, 2)
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#define MIPI_PHY_DATA_LANE_CTRL1_PIPE_ALL_EN (0x1f << 2)
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#define MIPI_PHY_DATA_LANE_CTRL1_PIPE_DELAY_MASK GENMASK(9, 7)
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#define MIPI_PHY_DATA_LANE_CTRL1_PIPE_DELAY_3 (3 << 7)
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#define MIPI_PHY_TCLK_MISS CSI_REG_D(0x10)
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#define MIPI_PHY_TCLK_MISS_CYCLES_MASK GENMASK(7, 0)
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#define MIPI_PHY_TCLK_MISS_CYCLES_5 (5 << 0)
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#define MIPI_PHY_TCLK_MISS_CYCLES_9 (9 << 0)
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#define MIPI_PHY_TCLK_SETTLE CSI_REG_D(0x14)
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#define MIPI_PHY_TCLK_SETTLE_CYCLES_MASK GENMASK(7, 0)
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#define MIPI_PHY_TCLK_SETTLE_CYCLES_24 (24 << 0)
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#define MIPI_PHY_TCLK_SETTLE_CYCLES_31 (31 << 0)
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#define MIPI_PHY_THS_EXIT CSI_REG_D(0x18)
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#define MIPI_PHY_THS_EXIT_CYCLES_MASK GENMASK(7, 0)
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#define MIPI_PHY_THS_EXIT_CYCLES_8 (8 << 0)
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#define MIPI_PHY_THS_SKIP CSI_REG_D(0x1c)
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#define MIPI_PHY_THS_SKIP_CYCLES_MASK GENMASK(7, 0)
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#define MIPI_PHY_THS_SKIP_CYCLES_10 (10 << 0)
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#define MIPI_PHY_THS_SETTLE CSI_REG_D(0x20)
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#define MIPI_PHY_THS_SETTLE_CYCLES_MASK GENMASK(7, 0)
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#define MIPI_PHY_TINIT CSI_REG_D(0x24)
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#define MIPI_PHY_TINIT_CYCLES_MASK GENMASK(31, 0)
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#define MIPI_PHY_TINIT_CYCLES_0X4E20 (0x4e20 << 0)
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#define MIPI_PHY_TULPS_C CSI_REG_D(0x28)
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#define MIPI_PHY_TULPS_C_CYCLES_MASK GENMASK(31, 0)
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#define MIPI_PHY_TULPS_C_CYCLES_4096 (4096 << 0)
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#define MIPI_PHY_TULPS_S CSI_REG_D(0x2c)
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#define MIPI_PHY_TULPS_S_CYCLES_MASK GENMASK(31, 0)
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#define MIPI_PHY_TULPS_S_CYCLES_256 (256 << 0)
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#define MIPI_PHY_TMBIAS CSI_REG_D(0x30)
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#define MIPI_PHY_TMBIAS_CYCLES_MASK GENMASK(31, 0)
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#define MIPI_PHY_TMBIAS_CYCLES_256 (256 << 0)
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#define MIPI_PHY_TLP_EN_W CSI_REG_D(0x34)
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#define MIPI_PHY_TLP_EN_W_CYCLES_MASK GENMASK(31, 0)
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#define MIPI_PHY_TLP_EN_W_CYCLES_12 (12 << 0)
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#define MIPI_PHY_TLPOK CSI_REG_D(0x38)
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#define MIPI_PHY_TLPOK_CYCLES_MASK GENMASK(31, 0)
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#define MIPI_PHY_TLPOK_CYCLES_256 (256 << 0)
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#define MIPI_PHY_TWD_INIT CSI_REG_D(0x3c)
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#define MIPI_PHY_TWD_INIT_DOG_MASK GENMASK(31, 0)
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#define MIPI_PHY_TWD_INIT_DOG_0X400000 (0x400000 << 0)
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#define MIPI_PHY_TWD_HS CSI_REG_D(0x40)
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#define MIPI_PHY_TWD_HS_DOG_MASK GENMASK(31, 0)
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#define MIPI_PHY_TWD_HS_DOG_0X400000 (0x400000 << 0)
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#define MIPI_PHY_CLK_LANE_STS CSI_REG_D(0x50)
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#define MIPI_PHY_DATA_LANE0_STS CSI_REG_D(0x54)
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#define MIPI_PHY_DATA_LANE1_STS CSI_REG_D(0x58)
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#define MIPI_PHY_DATA_LANE2_STS CSI_REG_D(0x5c)
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#define MIPI_PHY_DATA_LANE3_STS CSI_REG_D(0x60)
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#define MIPI_PHY_DESKEW_CTRL CSI_REG_D(0x7c)
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#define MIPI_PHY_DESKEW_CTRL_DEFAULT (0x86004005)
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#define MIPI_PHY_DESKEW_CTRL_EN_MASK BIT(31)
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#define MIPI_PHY_DESKEW_CTRL_EN BIT(31)
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#define MIPI_PHY_DESKEW_CTRL_DIS (0 << 31)
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#define MIPI_PHY_DESKEW_CTRL_1 CSI_REG_D(0x2AC)
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#define MIPI_PHY_DESKEW_CTRL_1_DEFAULT (0x710014)
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#define MIPI_PHY_DESKEW_CTRL_2 CSI_REG_D(0x2B0)
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#define MIPI_PHY_DESKEW_CTRL_2_DEFAULT (0x40050a)
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#define MIPI_PHY_DESKEW_CTRL_3 CSI_REG_D(0x2B4)
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#define MIPI_PHY_DESKEW_CTRL_3_DEFAULT (0x3001)
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#define MIPI_PHY_DESKEW_CTRL_4 CSI_REG_D(0x2BC)
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#define MIPI_PHY_DESKEW_CTRL_4_DEFAULT (0x440d)
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#define MIPI_PHY_DESKEW_CTRL_5 CSI_REG_D(0x2C0)
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#define MIPI_PHY_DESKEW_CTRL_5_DEFAULT (0x122ffff)
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#define MIPI_PHY_DESKEW_CTRL_6 CSI_REG_D(0x2D4)
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#define MIPI_PHY_DESKEW_CTRL_6_DEFAULT (0xdee48)
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#define MIPI_PHY_MUX_CTRL0 CSI_REG_D(0x284)
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#define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_MASK GENMASK(3, 0)
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#define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE0 (0 << 0)
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#define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE1 BIT(0)
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#define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE2 (2 << 0)
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#define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE3 (3 << 0)
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#define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE(x) ((x) << 0)
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#define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_MASK GENMASK(7, 4)
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#define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE0 (0 << 4)
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#define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE1 BIT(4)
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#define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE2 (2 << 4)
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#define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE3 (3 << 4)
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#define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE(x) ((x) << 4)
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#define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_MASK GENMASK(11, 8)
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#define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE0 (0 << 8)
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#define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE1 BIT(8)
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#define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE2 (2 << 8)
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#define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE3 (3 << 8)
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#define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE(x) ((x) << 8)
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#define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_MASK GENMASK(14, 12)
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#define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE0 (0 << 12)
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#define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE1 BIT(12)
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#define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE2 (2 << 12)
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#define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE3 (3 << 12)
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#define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE(x) ((x) << 12)
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#define MIPI_PHY_MUX_CTRL0_CLOCK_LANE_MASK GENMASK(17, 16)
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#define MIPI_PHY_MUX_CTRL0_CLOCK_LANE0 (0 << 16)
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#define MIPI_PHY_MUX_CTRL0_CLOCK_LANE1 (1 << 16)
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#define MIPI_PHY_MUX_CTRL0_CLOCK_LANE(x) ((x) << 16)
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#define MIPI_PHY_MUX_CTRL1 CSI_REG_D(0x288)
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#define MIPI_PHY_MUX_CTRL1_LANE3_SRC_MASK GENMASK(3, 0)
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#define MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN0 (0 << 0)
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#define MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN1 BIT(0)
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#define MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN2 (2 << 0)
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#define MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN3 (3 << 0)
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#define MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN(x) ((x) << 0)
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#define MIPI_PHY_MUX_CTRL1_LANE2_SRC_MASK GENMASK(7, 4)
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#define MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN0 (0 << 4)
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#define MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN1 BIT(4)
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#define MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN2 (2 << 4)
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#define MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN3 (3 << 4)
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#define MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN(x) ((x) << 4)
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#define MIPI_PHY_MUX_CTRL1_LANE1_SRC_MASK GENMASK(11, 8)
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#define MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN0 (0 << 8)
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#define MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN1 BIT(8)
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#define MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN2 (2 << 8)
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#define MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN3 (3 << 8)
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#define MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN(x) ((x) << 8)
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#define MIPI_PHY_MUX_CTRL1_LANE0_SRC_MASK GENMASK(14, 12)
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#define MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN0 (0 << 12)
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#define MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN1 BIT(12)
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#define MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN2 (2 << 12)
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#define MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN3 (3 << 12)
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#define MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN(x) ((x) << 12)
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#define MIPI_PHY_MUX_CTRL1_ANALOG_CLK0_MASK BIT(16)
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#define MIPI_PHY_MUX_CTRL1_ANALOG_CLK0_DPHY_SCNN (0 << 16)
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#define MIPI_PHY_MUX_CTRL1_ANALOG_CLK0_INPUT0 BIT(16)
|
|
#define MIPI_PHY_MUX_CTRL1_ANALOG_CLK1_MASK BIT(17)
|
|
#define MIPI_PHY_MUX_CTRL1_ANALOG_CLK1_DPHY_SCNN (0 << 17)
|
|
#define MIPI_PHY_MUX_CTRL1_ANALOG_CLK1_INPUT0 BIT(17)
|
|
#define MIPI_PHY_MUX_CTRL1_SEL_ANALOG_INPUT_CLK(x) ((x) << 18)
|
|
|
|
/* C3 CSI-2 HOST register */
|
|
#define CSI2_HOST_N_LANES CSI_REG_H(0x04)
|
|
#define CSI2_HOST_N_LANES_MASK GENMASK(1, 0)
|
|
#define CSI2_HOST_N_LANES_1 (0 << 0)
|
|
#define CSI2_HOST_N_LANES_2 BIT(0)
|
|
#define CSI2_HOST_N_LANES_3 (2 << 0)
|
|
#define CSI2_HOST_N_LANES_4 (3 << 0)
|
|
|
|
#define CSI2_HOST_ERR1 CSI_REG_H(0x20)
|
|
#define CSI2_HOST_ERR2 CSI_REG_H(0x24)
|
|
|
|
#define CSI2_HOST_CSI2_RESETN CSI_REG_H(0x10)
|
|
#define CSI2_HOST_CSI2_RESETN_MASK BIT(0)
|
|
#define CSI2_HOST_CSI2_RESETN_ACTIVE (0 << 0)
|
|
#define CSI2_HOST_CSI2_RESETN_EXIT BIT(0)
|
|
|
|
enum c4_csi_id {
|
|
C4_CSI_0,
|
|
C4_CSI_1,
|
|
C4_CSI_2,
|
|
C4_CSI_3,
|
|
C4_CSI_MAX
|
|
};
|
|
|
|
enum {
|
|
C4_CSI_PAD_SINK,
|
|
C4_CSI_PAD_SRC,
|
|
C4_CSI_PAD_MAX
|
|
};
|
|
|
|
#define C4_CSI_MAX_WIDTH 4656
|
|
#define C4_CSI_MIN_WIDTH 160
|
|
#define C4_CSI_MAX_HEIGHT 3496
|
|
#define C4_CSI_MIN_HEIGHT 120
|
|
#define C4_CSI_DEFAULT_WIDTH 1920
|
|
#define C4_CSI_DEFAULT_HEIGHT 1080
|
|
#define C4_CSI_DEFAULT_FMT MEDIA_BUS_FMT_SRGGB10_1X10
|
|
|
|
struct c4_csi_match_info {
|
|
enum c4_csi_id id;
|
|
char *clocks[C4_CSI_CLOCK_NUM_MAX];
|
|
u32 clock_num;
|
|
};
|
|
|
|
struct c4_csi_device {
|
|
struct device *dev;
|
|
void __iomem *aphy;
|
|
void __iomem *dphy;
|
|
void __iomem *host;
|
|
struct clk_bulk_data clks[C4_CSI_CLOCK_NUM_MAX];
|
|
|
|
struct v4l2_subdev sd;
|
|
struct media_pad pads[C4_CSI_PAD_MAX];
|
|
struct v4l2_async_notifier notifier;
|
|
struct media_pad *src_pad;
|
|
struct v4l2_mbus_config_mipi_csi2 bus;
|
|
|
|
const struct c4_csi_match_info *info;
|
|
struct proc_dir_entry *proc_entry;
|
|
u32 lane_rate_mbps;
|
|
};
|
|
|
|
static const u32 c4_csi_formats[] = {
|
|
MEDIA_BUS_FMT_SBGGR10_1X10,
|
|
MEDIA_BUS_FMT_SGBRG10_1X10,
|
|
MEDIA_BUS_FMT_SGRBG10_1X10,
|
|
MEDIA_BUS_FMT_SRGGB10_1X10,
|
|
MEDIA_BUS_FMT_SBGGR12_1X12,
|
|
MEDIA_BUS_FMT_SGBRG12_1X12,
|
|
MEDIA_BUS_FMT_SGRBG12_1X12,
|
|
MEDIA_BUS_FMT_SRGGB12_1X12,
|
|
MEDIA_BUS_FMT_UYVY8_2X8,
|
|
};
|
|
|
|
static void c4_csi_write(struct c4_csi_device *csi, u32 reg, u32 val)
|
|
{
|
|
void __iomem *addr;
|
|
|
|
switch (CSI_SUBMD(reg)) {
|
|
case SUBMD_APHY:
|
|
addr = csi->aphy + CSI_REG_ADDR(reg);
|
|
break;
|
|
case SUBMD_DPHY:
|
|
addr = csi->dphy + CSI_REG_ADDR(reg);
|
|
break;
|
|
case SUBMD_HOST:
|
|
addr = csi->host + CSI_REG_ADDR(reg);
|
|
break;
|
|
default:
|
|
dev_err(csi->dev, "Invalid sub-module: %lu\n", CSI_SUBMD(reg));
|
|
return;
|
|
}
|
|
|
|
writel(val, addr);
|
|
}
|
|
|
|
static u32 c4_csi_read(struct c4_csi_device *csi, u32 reg)
|
|
{
|
|
void __iomem *addr;
|
|
|
|
switch (CSI_SUBMD(reg)) {
|
|
case SUBMD_APHY:
|
|
addr = csi->aphy + CSI_REG_ADDR(reg);
|
|
break;
|
|
case SUBMD_DPHY:
|
|
addr = csi->dphy + CSI_REG_ADDR(reg);
|
|
break;
|
|
case SUBMD_HOST:
|
|
addr = csi->host + CSI_REG_ADDR(reg);
|
|
break;
|
|
default:
|
|
dev_err(csi->dev, "Invalid sub-module: %lu\n", CSI_SUBMD(reg));
|
|
return CSI_SUBMD(reg);
|
|
}
|
|
|
|
return readl(addr);
|
|
}
|
|
|
|
void c4_csi_update_bits(struct c4_csi_device *csi, u32 reg, u32 mask, u32 val)
|
|
{
|
|
u32 orig, tmp;
|
|
|
|
orig = c4_csi_read(csi, reg);
|
|
|
|
tmp = orig & ~mask;
|
|
tmp |= val & mask;
|
|
|
|
if (tmp != orig)
|
|
c4_csi_write(csi, reg, tmp);
|
|
}
|
|
|
|
static int c4_isp_calc_aphy_chn_ctrl(struct c4_csi_device *csi)
|
|
{
|
|
struct v4l2_mbus_config_mipi_csi2 *bus = &csi->bus;
|
|
u8 dphy_id = csi->info->id % 2 ? 1 : 0;
|
|
u8 dphy_id_anoth = csi->info->id % 2 ? 0 : 1;
|
|
u32 data_lane_flag;
|
|
u32 chn_ctrl = 0;
|
|
|
|
if (bus->num_data_lanes == 2 && bus->clock_lane < 2) {
|
|
data_lane_flag = bus->data_lanes[0] + bus->data_lanes[1];
|
|
|
|
if (data_lane_flag == 5) {
|
|
chn_ctrl = MIPI_PROC_DPHY_CTRL3_CH0_SEL_DPHY(dphy_id) |
|
|
MIPI_PROC_DPHY_CTRL3_CH1_SEL_DPHY(dphy_id) |
|
|
MIPI_PROC_DPHY_CTRL3_CH3_SEL_DPHY(dphy_id_anoth) |
|
|
MIPI_PROC_DPHY_CTRL3_CH4_SEL_DPHY(dphy_id_anoth);
|
|
} else if (data_lane_flag == 9) {
|
|
chn_ctrl = MIPI_PROC_DPHY_CTRL3_CH0_SEL_DPHY(dphy_id_anoth) |
|
|
MIPI_PROC_DPHY_CTRL3_CH1_SEL_DPHY(dphy_id_anoth) |
|
|
MIPI_PROC_DPHY_CTRL3_CH3_SEL_DPHY(dphy_id) |
|
|
MIPI_PROC_DPHY_CTRL3_CH4_SEL_DPHY(dphy_id);
|
|
} else {
|
|
dev_err(csi->dev, "Invalid data_lane_flag: %u\n", data_lane_flag);
|
|
return -EINVAL;
|
|
}
|
|
} else if (bus->num_data_lanes == 4 && bus->clock_lane < 2) {
|
|
chn_ctrl = MIPI_PROC_DPHY_CTRL3_CH0_SEL_DPHY(dphy_id) |
|
|
MIPI_PROC_DPHY_CTRL3_CH1_SEL_DPHY(dphy_id) |
|
|
MIPI_PROC_DPHY_CTRL3_CH3_SEL_DPHY(dphy_id) |
|
|
MIPI_PROC_DPHY_CTRL3_CH4_SEL_DPHY(dphy_id);
|
|
} else {
|
|
dev_err(csi->dev, "Invalid num_data_lanes: %u, clock_lane: %u\n",
|
|
bus->num_data_lanes, bus->clock_lane);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (bus->clock_lane == 0)
|
|
chn_ctrl |= MIPI_PROC_DPHY_CTRL3_CH2_SEL_DPHY(dphy_id) |
|
|
MIPI_PROC_DPHY_CTRL3_CH5_SEL_DPHY(dphy_id_anoth);
|
|
else
|
|
chn_ctrl |= MIPI_PROC_DPHY_CTRL3_CH2_SEL_DPHY(dphy_id_anoth) |
|
|
MIPI_PROC_DPHY_CTRL3_CH5_SEL_DPHY(dphy_id);
|
|
|
|
return chn_ctrl;
|
|
}
|
|
|
|
static int c4_csi_cfg_aphy(struct c4_csi_device *csi)
|
|
{
|
|
struct v4l2_mbus_config_mipi_csi2 *bus = &csi->bus;
|
|
int chn_ctrl;
|
|
|
|
chn_ctrl = c4_isp_calc_aphy_chn_ctrl(csi);
|
|
if (chn_ctrl == -EINVAL)
|
|
return -EINVAL;
|
|
|
|
c4_csi_write(csi, MIPI_PROC_DPHY_CTRL0,
|
|
MIPI_PROC_DPHY_CTRL0_HS_EQ_C_CTRL(2) |
|
|
MIPI_PROC_DPHY_CTRL0_HS_EQ_R_CTRL(2) |
|
|
MIPI_PROC_DPHY_CTRL0_HS_D2S_CUR_CTRL(3) |
|
|
MIPI_PROC_DPHY_CTRL0_HS_EQ_RHALF_EN(0) |
|
|
MIPI_PROC_DPHY_CTRL0_HS_EQ_MAINMAX(0) |
|
|
MIPI_PROC_DPHY_CTRL0_HS_EQ_PATA_CUR_CTRL(5) |
|
|
MIPI_PROC_DPHY_CTRL0_HS_EQ_ZATA_CUR_CTRL(6) |
|
|
MIPI_PROC_DPHY_CTRL0_LP_COMP_CUR_CTRL(3) |
|
|
MIPI_PROC_DPHY_CTRL0_LP_VTH_CTRL(2) |
|
|
MIPI_PROC_DPHY_CTRL0_LP_VTL_CTRL(4));
|
|
|
|
c4_csi_write(csi, MIPI_PROC_DPHY_CTRL1,
|
|
MIPI_PROC_DPHY_CTRL1_RTERN_TRIMED_VAL(7));
|
|
|
|
if (bus->num_data_lanes == 2)
|
|
c4_csi_write(csi, MIPI_PROC_DPHY_CTRL2,
|
|
MIPI_PROC_DPHY_CTRL2_LANE3_CLK_SRC_SEL(1) |
|
|
MIPI_PROC_DPHY_CTRL2_LANE4_CLK_SRC_SEL(1));
|
|
else
|
|
c4_csi_write(csi, MIPI_PROC_DPHY_CTRL2,
|
|
MIPI_PROC_DPHY_CTRL2_LANE3_CLK_SRC_SEL(0) |
|
|
MIPI_PROC_DPHY_CTRL2_LANE4_CLK_SRC_SEL(0));
|
|
|
|
c4_csi_write(csi, MIPI_PROC_DPHY_CTRL3, chn_ctrl);
|
|
|
|
udelay(1);
|
|
|
|
c4_csi_update_bits(csi, MIPI_PROC_DPHY_CTRL0,
|
|
MIPI_PROC_DPHY_CTRL0_CSI_TOP_EN_MASK,
|
|
MIPI_PROC_DPHY_CTRL0_CSI_TOP_EN);
|
|
return 0;
|
|
}
|
|
|
|
static void c4_csi_cfg_lanes(struct c4_csi_device *csi)
|
|
{
|
|
struct v4l2_mbus_config_mipi_csi2 *bus = &csi->bus;
|
|
u32 sfen0_src_lane = 0xf;
|
|
u32 sfen1_src_lane = 0xf;
|
|
u32 sfen2_src_lane = 0xf;
|
|
u32 sfen3_src_lane = 0xf;
|
|
u32 data_lane0_src = 0xf;
|
|
u32 data_lane1_src = 0xf;
|
|
u32 data_lane2_src = 0xf;
|
|
u32 data_lane3_src = 0xf;
|
|
u32 clk_lane_select;
|
|
u32 clk_lane_src;
|
|
|
|
for (unsigned int i = 0; i < bus->num_data_lanes; i++) {
|
|
if (i == 0) {
|
|
sfen0_src_lane = bus->data_lanes[0] - 2;
|
|
} else if (i == 1) {
|
|
sfen1_src_lane = bus->data_lanes[1] - 2;
|
|
} else if (i == 2) {
|
|
sfen2_src_lane = bus->data_lanes[2] - 2;
|
|
} else if (i == 3) {
|
|
sfen3_src_lane = bus->data_lanes[3] - 2;
|
|
} else {
|
|
dev_err(csi->dev, "Invalid num_data_lanes: %u\n",
|
|
bus->num_data_lanes);
|
|
return;
|
|
}
|
|
|
|
if (bus->data_lanes[i] == 2)
|
|
data_lane0_src = i;
|
|
else if (bus->data_lanes[i] == 3)
|
|
data_lane1_src = i;
|
|
else if (bus->data_lanes[i] == 4)
|
|
data_lane2_src = i;
|
|
else if (bus->data_lanes[i] == 5)
|
|
data_lane3_src = i;
|
|
else {
|
|
dev_err(csi->dev, "Invalid data_lanes[%u]: %u\n",
|
|
i, bus->data_lanes[i]);
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (bus->clock_lane == 0) {
|
|
clk_lane_select = MIPI_PHY_MUX_CTRL0_CLOCK_LANE0;
|
|
clk_lane_src = MIPI_PHY_MUX_CTRL1_ANALOG_CLK0_DPHY_SCNN |
|
|
MIPI_PHY_MUX_CTRL1_ANALOG_CLK1_INPUT0;
|
|
} else if (bus->clock_lane == 1) {
|
|
clk_lane_select = MIPI_PHY_MUX_CTRL0_CLOCK_LANE1;
|
|
clk_lane_src = MIPI_PHY_MUX_CTRL1_ANALOG_CLK1_DPHY_SCNN |
|
|
MIPI_PHY_MUX_CTRL1_ANALOG_CLK0_INPUT0;
|
|
} else {
|
|
dev_err(csi->dev, "Invalid clock_lane %u\n", bus->clock_lane);
|
|
return;
|
|
}
|
|
|
|
c4_csi_write(csi, MIPI_PHY_MUX_CTRL0,
|
|
MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE(sfen0_src_lane) |
|
|
MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE(sfen1_src_lane) |
|
|
MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE(sfen2_src_lane) |
|
|
MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE(sfen3_src_lane) |
|
|
clk_lane_select);
|
|
|
|
c4_csi_write(csi, MIPI_PHY_MUX_CTRL1,
|
|
MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN(data_lane0_src) |
|
|
MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN(data_lane1_src) |
|
|
MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN(data_lane2_src) |
|
|
MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN(data_lane3_src) |
|
|
MIPI_PHY_MUX_CTRL1_SEL_ANALOG_INPUT_CLK(bus->clock_lane) |
|
|
clk_lane_src);
|
|
}
|
|
|
|
static void c4_csi_cfg_deskew(struct c4_csi_device *csi)
|
|
{
|
|
c4_csi_write(csi, MIPI_PHY_DESKEW_CTRL, MIPI_PHY_DESKEW_CTRL_DEFAULT);
|
|
c4_csi_write(csi, MIPI_PHY_DESKEW_CTRL_1, MIPI_PHY_DESKEW_CTRL_1_DEFAULT);
|
|
c4_csi_write(csi, MIPI_PHY_DESKEW_CTRL_2, MIPI_PHY_DESKEW_CTRL_2_DEFAULT);
|
|
c4_csi_write(csi, MIPI_PHY_DESKEW_CTRL_3, MIPI_PHY_DESKEW_CTRL_3_DEFAULT);
|
|
c4_csi_write(csi, MIPI_PHY_DESKEW_CTRL_4, MIPI_PHY_DESKEW_CTRL_4_DEFAULT);
|
|
c4_csi_write(csi, MIPI_PHY_DESKEW_CTRL_5, MIPI_PHY_DESKEW_CTRL_5_DEFAULT);
|
|
c4_csi_write(csi, MIPI_PHY_DESKEW_CTRL_6, MIPI_PHY_DESKEW_CTRL_6_DEFAULT);
|
|
|
|
c4_csi_update_bits(csi, MIPI_PROC_DPHY_CTRL3,
|
|
MIPI_PROC_DPHY_CTRL3_SKEW_FROM_DPHY_MASK,
|
|
MIPI_PROC_DPHY_CTRL3_SKEW_FROM_DPHY_EN);
|
|
}
|
|
|
|
static void c4_csi_cfg_dphy(struct c4_csi_device *csi, s64 rate)
|
|
{
|
|
u32 val;
|
|
u32 settle;
|
|
|
|
/* Calculate the high speed settle */
|
|
val = div64_s64(1000000000, rate);
|
|
//val = DIV_ROUND_UP(1000000000, rate);
|
|
settle = (16 * val + 230) / 10;
|
|
|
|
c4_csi_update_bits(csi, MIPI_PHY_CTRL,
|
|
MIPI_PHY_CTRL_SOFT_RESET_MASK,
|
|
MIPI_PHY_CTRL_SOFT_RESET_ACTIVE);
|
|
c4_csi_update_bits(csi, MIPI_PHY_CTRL,
|
|
MIPI_PHY_CTRL_SOFT_RESET_MASK,
|
|
MIPI_PHY_CTRL_SOFT_RESET_EXIT);
|
|
|
|
c4_csi_write(csi, MIPI_PHY_CLK_LANE_CTRL,
|
|
MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS_8 |
|
|
MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_EN |
|
|
MIPI_PHY_CLK_LANE_CTRL_ALIGN_RD_DLY_4 |
|
|
MIPI_PHY_CLK_LANE_CTRL_ALIGN_EN);
|
|
|
|
c4_csi_write(csi, MIPI_PHY_TCLK_MISS, MIPI_PHY_TCLK_MISS_CYCLES_9);
|
|
c4_csi_write(csi, MIPI_PHY_TCLK_SETTLE, MIPI_PHY_TCLK_SETTLE_CYCLES_31);
|
|
c4_csi_write(csi, MIPI_PHY_THS_EXIT, MIPI_PHY_THS_EXIT_CYCLES_8);
|
|
c4_csi_write(csi, MIPI_PHY_THS_SETTLE, settle);
|
|
c4_csi_write(csi, MIPI_PHY_TINIT, MIPI_PHY_TINIT_CYCLES_0X4E20);
|
|
c4_csi_write(csi, MIPI_PHY_TMBIAS, MIPI_PHY_TMBIAS_CYCLES_256);
|
|
c4_csi_write(csi, MIPI_PHY_TULPS_C, MIPI_PHY_TULPS_C_CYCLES_4096);
|
|
c4_csi_write(csi, MIPI_PHY_TULPS_S, MIPI_PHY_TULPS_S_CYCLES_256);
|
|
c4_csi_write(csi, MIPI_PHY_TLP_EN_W, MIPI_PHY_TLP_EN_W_CYCLES_12);
|
|
c4_csi_write(csi, MIPI_PHY_TLPOK, MIPI_PHY_TLPOK_CYCLES_256);
|
|
c4_csi_write(csi, MIPI_PHY_TWD_INIT, MIPI_PHY_TWD_INIT_DOG_0X400000);
|
|
c4_csi_write(csi, MIPI_PHY_TWD_HS, MIPI_PHY_TWD_HS_DOG_0X400000);
|
|
|
|
c4_csi_write(csi, MIPI_PHY_DATA_LANE_CTRL1,
|
|
MIPI_PHY_DATA_LANE_CTRL1_INSERT_ERRESC |
|
|
MIPI_PHY_DATA_LANE_CTRL1_HS_SYNC_CHK_EN |
|
|
MIPI_PHY_DATA_LANE_CTRL1_PIPE_ALL_EN |
|
|
MIPI_PHY_DATA_LANE_CTRL1_PIPE_DELAY_3);
|
|
|
|
c4_csi_cfg_lanes(csi);
|
|
|
|
c4_csi_cfg_deskew(csi);
|
|
|
|
/* Enable digital data and clock lanes */
|
|
c4_csi_write(csi, MIPI_PHY_CTRL,
|
|
MIPI_PHY_CTRL_DATA_LANE0_EN |
|
|
MIPI_PHY_CTRL_DATA_LANE1_EN |
|
|
MIPI_PHY_CTRL_DATA_LANE2_EN |
|
|
MIPI_PHY_CTRL_DATA_LANE3_EN |
|
|
MIPI_PHY_CTRL_CLOCK_LANE_EN);
|
|
}
|
|
|
|
static void c4_csi_cfg_host(struct c4_csi_device *csi)
|
|
{
|
|
/* Reset CSI-2 controller output */
|
|
c4_csi_write(csi, CSI2_HOST_CSI2_RESETN, CSI2_HOST_CSI2_RESETN_ACTIVE);
|
|
c4_csi_write(csi, CSI2_HOST_CSI2_RESETN, CSI2_HOST_CSI2_RESETN_EXIT);
|
|
|
|
/* Set data lane number */
|
|
c4_csi_write(csi, CSI2_HOST_N_LANES, csi->bus.num_data_lanes - 1);
|
|
}
|
|
|
|
static int c4_csi_start_stream(struct c4_csi_device *csi,
|
|
struct v4l2_subdev *src_sd)
|
|
{
|
|
s64 link_freq;
|
|
s64 lane_rate;
|
|
|
|
link_freq = v4l2_get_link_freq(src_sd->ctrl_handler, 0, 0);
|
|
if (link_freq < 0) {
|
|
dev_err(csi->dev,
|
|
"Unable to obtain link frequency: %lld\n", link_freq);
|
|
return link_freq;
|
|
}
|
|
|
|
lane_rate = link_freq * 2;
|
|
csi->lane_rate_mbps = div64_u64(lane_rate, 1000000);
|
|
|
|
c4_csi_cfg_aphy(csi);
|
|
c4_csi_cfg_dphy(csi, lane_rate);
|
|
c4_csi_cfg_host(csi);
|
|
|
|
dev_info(csi->dev, "CSI-2 config bps: %lld\n", lane_rate);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int c4_csi_stop_stream(struct c4_csi_device *csi)
|
|
{
|
|
/* Disable digital data and clock lanes */
|
|
c4_csi_write(csi, MIPI_PHY_CTRL,
|
|
MIPI_PHY_CTRL_DATA_LANE0_DIS |
|
|
MIPI_PHY_CTRL_DATA_LANE1_DIS |
|
|
MIPI_PHY_CTRL_DATA_LANE2_DIS |
|
|
MIPI_PHY_CTRL_DATA_LANE3_DIS |
|
|
MIPI_PHY_CTRL_CLOCK_LANE_DIS);
|
|
return 0;
|
|
}
|
|
|
|
static int c4_csi_enable_streams(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_state *state,
|
|
u32 pad, u64 streams_mask)
|
|
{
|
|
struct c4_csi_device *csi = v4l2_get_subdevdata(sd);
|
|
struct media_pad *sink_pad;
|
|
struct v4l2_subdev *src_sd;
|
|
int ret;
|
|
|
|
sink_pad = &csi->pads[C4_CSI_PAD_SINK];
|
|
csi->src_pad = media_pad_remote_pad_unique(sink_pad);
|
|
if (IS_ERR(csi->src_pad)) {
|
|
dev_dbg(csi->dev, "Failed to get source pad for CSI-2\n");
|
|
return -EPIPE;
|
|
}
|
|
|
|
src_sd = media_entity_to_v4l2_subdev(csi->src_pad->entity);
|
|
|
|
pm_runtime_resume_and_get(csi->dev);
|
|
|
|
c4_csi_start_stream(csi, src_sd);
|
|
|
|
ret = v4l2_subdev_enable_streams(src_sd, csi->src_pad->index, BIT(0));
|
|
if (ret) {
|
|
pm_runtime_put(csi->dev);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int c4_csi_disable_streams(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_state *state,
|
|
u32 pad, u64 streams_mask)
|
|
{
|
|
struct c4_csi_device *csi = v4l2_get_subdevdata(sd);
|
|
struct v4l2_subdev *src_sd;
|
|
|
|
c4_csi_stop_stream(csi);
|
|
|
|
if (csi->src_pad) {
|
|
src_sd = media_entity_to_v4l2_subdev(csi->src_pad->entity);
|
|
v4l2_subdev_disable_streams(src_sd, csi->src_pad->index,
|
|
BIT(0));
|
|
}
|
|
csi->src_pad = NULL;
|
|
|
|
pm_runtime_put(csi->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int c4_csi_enum_mbus_code(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_state *state,
|
|
struct v4l2_subdev_mbus_code_enum *code)
|
|
{
|
|
struct v4l2_mbus_framefmt *fmt;
|
|
|
|
switch (code->pad) {
|
|
case C4_CSI_PAD_SINK:
|
|
if (code->index >= ARRAY_SIZE(c4_csi_formats))
|
|
return -EINVAL;
|
|
|
|
code->code = c4_csi_formats[code->index];
|
|
break;
|
|
case C4_CSI_PAD_SRC:
|
|
if (code->index)
|
|
return -EINVAL;
|
|
|
|
fmt = v4l2_subdev_state_get_format(state, code->pad);
|
|
code->code = fmt->code;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int c4_csi_set_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_state *state,
|
|
struct v4l2_subdev_format *format)
|
|
{
|
|
struct v4l2_mbus_framefmt *fmt;
|
|
unsigned int i;
|
|
|
|
if (format->pad != C4_CSI_PAD_SINK)
|
|
return v4l2_subdev_get_fmt(sd, state, format);
|
|
|
|
fmt = v4l2_subdev_state_get_format(state, format->pad);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(c4_csi_formats); i++) {
|
|
if (format->format.code == c4_csi_formats[i]) {
|
|
fmt->code = c4_csi_formats[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (i == ARRAY_SIZE(c4_csi_formats))
|
|
fmt->code = c4_csi_formats[0];
|
|
|
|
fmt->width = clamp_t(u32, format->format.width,
|
|
C4_CSI_MIN_WIDTH, C4_CSI_MAX_WIDTH);
|
|
fmt->height = clamp_t(u32, format->format.height,
|
|
C4_CSI_MIN_HEIGHT, C4_CSI_MAX_HEIGHT);
|
|
fmt->colorspace = V4L2_COLORSPACE_RAW;
|
|
fmt->xfer_func = V4L2_XFER_FUNC_NONE;
|
|
fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
|
|
fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
|
|
|
|
format->format = *fmt;
|
|
|
|
/* Synchronize the format to source pad */
|
|
fmt = v4l2_subdev_state_get_format(state, C4_CSI_PAD_SRC);
|
|
*fmt = format->format;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int c4_csi_init_state(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_state *state)
|
|
{
|
|
struct v4l2_mbus_framefmt *sink_fmt;
|
|
struct v4l2_mbus_framefmt *src_fmt;
|
|
|
|
sink_fmt = v4l2_subdev_state_get_format(state, C4_CSI_PAD_SINK);
|
|
src_fmt = v4l2_subdev_state_get_format(state, C4_CSI_PAD_SRC);
|
|
|
|
sink_fmt->width = C4_CSI_DEFAULT_WIDTH;
|
|
sink_fmt->height = C4_CSI_DEFAULT_HEIGHT;
|
|
sink_fmt->field = V4L2_FIELD_NONE;
|
|
sink_fmt->code = C4_CSI_DEFAULT_FMT;
|
|
sink_fmt->colorspace = V4L2_COLORSPACE_RAW;
|
|
sink_fmt->xfer_func = V4L2_XFER_FUNC_NONE;
|
|
sink_fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
|
|
sink_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
|
|
|
|
*src_fmt = *sink_fmt;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct v4l2_subdev_pad_ops c4_csi_pad_ops = {
|
|
.enum_mbus_code = c4_csi_enum_mbus_code,
|
|
.get_fmt = v4l2_subdev_get_fmt,
|
|
.set_fmt = c4_csi_set_fmt,
|
|
.enable_streams = c4_csi_enable_streams,
|
|
.disable_streams = c4_csi_disable_streams,
|
|
};
|
|
|
|
static const struct v4l2_subdev_ops c4_csi_subdev_ops = {
|
|
.pad = &c4_csi_pad_ops,
|
|
};
|
|
|
|
static const struct v4l2_subdev_internal_ops c4_csi_internal_ops = {
|
|
.init_state = c4_csi_init_state,
|
|
};
|
|
|
|
/* Media entity operations */
|
|
static const struct media_entity_operations c4_csi_entity_ops = {
|
|
.link_validate = v4l2_subdev_link_validate,
|
|
};
|
|
|
|
/* PM runtime */
|
|
|
|
static int c4_csi_runtime_suspend(struct device *dev)
|
|
{
|
|
struct c4_csi_device *csi = dev_get_drvdata(dev);
|
|
|
|
clk_bulk_disable_unprepare(csi->info->clock_num, csi->clks);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int c4_csi_runtime_resume(struct device *dev)
|
|
{
|
|
struct c4_csi_device *csi = dev_get_drvdata(dev);
|
|
|
|
return clk_bulk_prepare_enable(csi->info->clock_num, csi->clks);
|
|
}
|
|
|
|
static const struct dev_pm_ops c4_csi_pm_ops = {
|
|
SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
RUNTIME_PM_OPS(c4_csi_runtime_suspend,
|
|
c4_csi_runtime_resume, NULL)
|
|
};
|
|
|
|
/* Probe/remove & platform driver */
|
|
|
|
static int c4_csi_subdev_init(struct c4_csi_device *csi)
|
|
{
|
|
struct v4l2_subdev *sd = &csi->sd;
|
|
int ret;
|
|
|
|
v4l2_subdev_init(sd, &c4_csi_subdev_ops);
|
|
sd->owner = THIS_MODULE;
|
|
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
|
|
sd->internal_ops = &c4_csi_internal_ops;
|
|
snprintf(sd->name, sizeof(sd->name), "%s", C4_CSI_SUBDEV_NAME);
|
|
|
|
sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
|
|
sd->entity.ops = &c4_csi_entity_ops;
|
|
|
|
sd->dev = csi->dev;
|
|
v4l2_set_subdevdata(sd, csi);
|
|
|
|
csi->pads[C4_CSI_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
|
|
csi->pads[C4_CSI_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
|
|
ret = media_entity_pads_init(&sd->entity, C4_CSI_PAD_MAX,
|
|
csi->pads);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = v4l2_subdev_init_finalize(sd);
|
|
if (ret) {
|
|
media_entity_cleanup(&sd->entity);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void c4_csi_subdev_deinit(struct c4_csi_device *csi)
|
|
{
|
|
v4l2_subdev_cleanup(&csi->sd);
|
|
media_entity_cleanup(&csi->sd.entity);
|
|
}
|
|
|
|
/* Subdev notifier register */
|
|
static int c4_csi_notify_bound(struct v4l2_async_notifier *notifier,
|
|
struct v4l2_subdev *sd,
|
|
struct v4l2_async_connection *asc)
|
|
{
|
|
struct c4_csi_device *csi = v4l2_get_subdevdata(notifier->sd);
|
|
struct media_pad *sink = &csi->sd.entity.pads[C4_CSI_PAD_SINK];
|
|
|
|
return v4l2_create_fwnode_links_to_pad(sd, sink, MEDIA_LNK_FL_ENABLED |
|
|
MEDIA_LNK_FL_IMMUTABLE);
|
|
}
|
|
|
|
static const struct v4l2_async_notifier_operations c4_csi_notify_ops = {
|
|
.bound = c4_csi_notify_bound,
|
|
};
|
|
|
|
static int c4_csi_async_register(struct c4_csi_device *csi)
|
|
{
|
|
struct v4l2_fwnode_endpoint vep = {
|
|
.bus_type = V4L2_MBUS_CSI2_DPHY,
|
|
};
|
|
struct v4l2_async_connection *asc;
|
|
struct fwnode_handle *ep;
|
|
int ret;
|
|
|
|
v4l2_async_subdev_nf_init(&csi->notifier, &csi->sd);
|
|
|
|
ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi->dev), 0, 0,
|
|
FWNODE_GRAPH_ENDPOINT_NEXT);
|
|
if (!ep)
|
|
return -ENOTCONN;
|
|
|
|
ret = v4l2_fwnode_endpoint_parse(ep, &vep);
|
|
if (ret)
|
|
goto err_put_handle;
|
|
|
|
csi->bus = vep.bus.mipi_csi2;
|
|
|
|
asc = v4l2_async_nf_add_fwnode_remote(&csi->notifier, ep,
|
|
struct v4l2_async_connection);
|
|
if (IS_ERR(asc)) {
|
|
ret = PTR_ERR(asc);
|
|
goto err_put_handle;
|
|
}
|
|
|
|
csi->notifier.ops = &c4_csi_notify_ops;
|
|
ret = v4l2_async_nf_register(&csi->notifier);
|
|
if (ret)
|
|
goto err_cleanup_nf;
|
|
|
|
ret = v4l2_async_register_subdev(&csi->sd);
|
|
if (ret)
|
|
goto err_unregister_nf;
|
|
|
|
fwnode_handle_put(ep);
|
|
|
|
return 0;
|
|
|
|
err_unregister_nf:
|
|
v4l2_async_nf_unregister(&csi->notifier);
|
|
err_cleanup_nf:
|
|
v4l2_async_nf_cleanup(&csi->notifier);
|
|
err_put_handle:
|
|
fwnode_handle_put(ep);
|
|
return ret;
|
|
}
|
|
|
|
static void c3_mipi_csi_async_unregister(struct c4_csi_device *csi)
|
|
{
|
|
v4l2_async_unregister_subdev(&csi->sd);
|
|
v4l2_async_nf_unregister(&csi->notifier);
|
|
v4l2_async_nf_cleanup(&csi->notifier);
|
|
}
|
|
|
|
static int c4_csi_ioremap_resource(struct c4_csi_device *csi)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(csi->dev);
|
|
struct resource *res;
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aphy");
|
|
if (!res)
|
|
return -EINVAL;
|
|
|
|
csi->aphy = devm_ioremap(csi->dev, res->start, resource_size(res));
|
|
if (!csi->aphy)
|
|
return -ENOMEM;
|
|
|
|
csi->dphy = devm_platform_ioremap_resource_byname(pdev, "dphy");
|
|
if (IS_ERR(csi->dphy))
|
|
return PTR_ERR(csi->dphy);
|
|
|
|
csi->host = devm_platform_ioremap_resource_byname(pdev, "host");
|
|
if (IS_ERR(csi->host))
|
|
return PTR_ERR(csi->host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int c4_csi_get_clocks(struct c4_csi_device *csi)
|
|
{
|
|
const struct c4_csi_match_info *info = csi->info;
|
|
|
|
for (unsigned int i = 0; i < info->clock_num; i++)
|
|
csi->clks[i].id = info->clocks[i];
|
|
|
|
return devm_clk_bulk_get(csi->dev, info->clock_num, csi->clks);
|
|
}
|
|
|
|
static u32 *c4_csi_hw_info(struct c4_csi_device *csi)
|
|
{
|
|
static u32 debuginfo[15];
|
|
|
|
debuginfo[0] = c4_csi_read(csi, MIPI_PHY_CLK_LANE_STS);
|
|
debuginfo[1] = c4_csi_read(csi, MIPI_PHY_DATA_LANE0_STS);
|
|
debuginfo[2] = c4_csi_read(csi, MIPI_PHY_DATA_LANE1_STS);
|
|
debuginfo[3] = c4_csi_read(csi, MIPI_PHY_DATA_LANE2_STS);
|
|
debuginfo[4] = c4_csi_read(csi, MIPI_PHY_DATA_LANE3_STS);
|
|
debuginfo[5] = c4_csi_read(csi, MIPI_PHY_MUX_CTRL0);
|
|
debuginfo[6] = c4_csi_read(csi, MIPI_PHY_MUX_CTRL1);
|
|
debuginfo[7] = c4_csi_read(csi, MIPI_PROC_DPHY_CTRL0);
|
|
debuginfo[8] = c4_csi_read(csi, MIPI_PROC_DPHY_CTRL1);
|
|
debuginfo[9] = c4_csi_read(csi, MIPI_PROC_DPHY_CTRL2);
|
|
debuginfo[10] = c4_csi_read(csi, MIPI_PROC_DPHY_CTRL3);
|
|
debuginfo[11] = 0;
|
|
debuginfo[12] = 0;
|
|
debuginfo[13] = c4_csi_read(csi, CSI2_HOST_ERR1);
|
|
debuginfo[14] = c4_csi_read(csi, CSI2_HOST_ERR2);
|
|
|
|
return debuginfo;
|
|
}
|
|
|
|
static int c4_csi_proc_show(struct seq_file *m, void *v)
|
|
{
|
|
struct c4_csi_device *csi = m->private;
|
|
u32 *mipi_info = c4_csi_hw_info(csi);
|
|
|
|
seq_printf(m, "\n*******************CSIPHY MODULE PARAM*******************\n");
|
|
seq_printf(m, " ------- PubAttr Info ------- \n");
|
|
seq_printf(m, "LaneCnt\tLaneBps\t\n");
|
|
seq_printf(m, "%u \t %u \t \n\n",
|
|
csi->bus.num_data_lanes, csi->lane_rate_mbps);
|
|
|
|
seq_printf(m, " ------- Csiphy Info ------- \n");
|
|
seq_printf(m, "clk\tLane1\tLane2\tLane3\tLane4\n");
|
|
seq_printf(m, "0x%02x \t 0x%02x \t 0x%02x \t 0x%02x \t 0x%02x \n\n",
|
|
mipi_info[0], mipi_info[1], mipi_info[2],
|
|
mipi_info[3], mipi_info[4]);
|
|
|
|
seq_printf(m, " ------- Dphy Cfg ------- \n");
|
|
seq_printf(m, "MIPI_PHY_MUX_CTRL0\tMIPI_PHY_MUX_CTRL1\t\n");
|
|
seq_printf(m, "0x%02x \t\t\t 0x%02x \n\n", mipi_info[5], mipi_info[6]);
|
|
|
|
seq_printf(m, " ------- Aphy Cfg ------- \n");
|
|
seq_printf(m, "MIPI_CSI_2M_PHY2_CNTL1\tMIPI_CSI_2M_PHY2_CNTL2\t"
|
|
"MIPI_CSI_2M_PHY2_CNTL3\t\n"
|
|
"MIPI_CSI_2M_PHY2_CNTL4\tMIPI_CSI_2M_PHY2_CNTL5\t"
|
|
"MIPI_CSI_2M_PHY2_CNTL6\t\n");
|
|
seq_printf(m, "0x%02x \t\t 0x%02x \t\t 0x%02x \t\n"
|
|
"0x%02x \t\t 0x%02x \t\t 0x%02x \t\t \n\n",
|
|
mipi_info[7], mipi_info[8], mipi_info[9],
|
|
mipi_info[10], mipi_info[11], mipi_info[12]);
|
|
|
|
seq_printf(m, "CSI2_host_err1\tCSI2_host_err2\n");
|
|
seq_printf(m, "0x%02x \t\t 0x%02x \n\n", mipi_info[13], mipi_info[14]);
|
|
seq_printf(m, "******************* PROC END *******************\n\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int c4_csi_debug_open(struct inode *inode, struct file *file)
|
|
{
|
|
#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
|
|
return single_open(file, c4_csi_proc_show, pde_data(inode));
|
|
#else
|
|
return single_open(file, c4_csi_proc_show, PDE_DATA(inode));
|
|
#endif
|
|
}
|
|
|
|
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)
|
|
static const struct proc_ops c4_csi_proc_file_ops = {
|
|
.proc_open = c4_csi_debug_open,
|
|
.proc_read = seq_read,
|
|
.proc_lseek = seq_lseek,
|
|
.proc_release = single_release,
|
|
};
|
|
#else
|
|
static const struct file_operations c4_csi_proc_file_ops = {
|
|
.open = c4_csi_debug_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
};
|
|
#endif
|
|
|
|
static int c4_csi_proc_init(struct c4_csi_device *csi)
|
|
{
|
|
char name[16];
|
|
|
|
snprintf(name, sizeof(name), "csi%u", csi->info->id);
|
|
csi->proc_entry = proc_create_data(name, 0644, NULL,
|
|
&c4_csi_proc_file_ops, csi);
|
|
if (!csi->proc_entry) {
|
|
dev_err(csi->dev, "csi%u create proc failed\n", csi->info->id);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void c4_csi_proc_remove(struct c4_csi_device *csi)
|
|
{
|
|
if (csi->proc_entry) {
|
|
proc_remove(csi->proc_entry);
|
|
csi->proc_entry = NULL;
|
|
}
|
|
}
|
|
|
|
static int c4_csi_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct c4_csi_device *csi;
|
|
int ret;
|
|
|
|
csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
|
|
if (!csi)
|
|
return -ENOMEM;
|
|
|
|
csi->info = of_device_get_match_data(dev);
|
|
csi->dev = dev;
|
|
|
|
ret = c4_csi_ioremap_resource(csi);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to ioremap resource\n");
|
|
|
|
ret = c4_csi_get_clocks(csi);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to get clocks\n");
|
|
|
|
platform_set_drvdata(pdev, csi);
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
ret = c4_csi_subdev_init(csi);
|
|
if (ret)
|
|
goto err_disable_runtime_pm;
|
|
|
|
ret = c4_csi_async_register(csi);
|
|
if (ret)
|
|
goto err_deinit_subdev;
|
|
|
|
ret = c4_csi_proc_init(csi);
|
|
if (ret)
|
|
goto err_async_unregister;
|
|
|
|
return 0;
|
|
|
|
err_async_unregister:
|
|
c3_mipi_csi_async_unregister(csi);
|
|
|
|
err_deinit_subdev:
|
|
c4_csi_subdev_deinit(csi);
|
|
err_disable_runtime_pm:
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
static void c4_csi_remove(struct platform_device *pdev)
|
|
{
|
|
struct c4_csi_device *csi = platform_get_drvdata(pdev);
|
|
|
|
c4_csi_proc_remove(csi);
|
|
c3_mipi_csi_async_unregister(csi);
|
|
c4_csi_subdev_deinit(csi);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
};
|
|
|
|
static const struct c4_csi_match_info c4_csi_info_0 = {
|
|
.id = C4_CSI_0,
|
|
.clocks = {"phy"},
|
|
.clock_num = 1,
|
|
};
|
|
|
|
static const struct c4_csi_match_info c4_csi_info_1 = {
|
|
.id = C4_CSI_1,
|
|
.clocks = {"phy"},
|
|
.clock_num = 1,
|
|
};
|
|
|
|
static const struct c4_csi_match_info c4_csi_info_2 = {
|
|
.id = C4_CSI_2,
|
|
.clocks = {"phy"},
|
|
.clock_num = 1,
|
|
};
|
|
|
|
static const struct c4_csi_match_info c4_csi_info_3 = {
|
|
.id = C4_CSI_3,
|
|
.clocks = {"phy"},
|
|
.clock_num = 1,
|
|
};
|
|
|
|
static const struct of_device_id c4_csi_of_match[] = {
|
|
{
|
|
.compatible = "amlogic,csi2-0",
|
|
.data = &c4_csi_info_0,
|
|
}, {
|
|
.compatible = "amlogic,csi2-1",
|
|
.data = &c4_csi_info_1,
|
|
}, {
|
|
.compatible = "amlogic,csi2-2",
|
|
.data = &c4_csi_info_2,
|
|
}, {
|
|
.compatible = "amlogic,csi2-3",
|
|
.data = &c4_csi_info_3,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, c4_csi_of_match);
|
|
|
|
static struct platform_driver c4_csi_driver = {
|
|
.probe = c4_csi_probe,
|
|
.remove = c4_csi_remove,
|
|
.driver = {
|
|
.name = "c4-csi",
|
|
.of_match_table = c4_csi_of_match,
|
|
.pm = pm_ptr(&c4_csi_pm_ops),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(c4_csi_driver);
|
|
|
|
MODULE_AUTHOR("Keke Li <[email protected]>");
|
|
MODULE_DESCRIPTION("Amlogic C4 CSI-2 receiver");
|
|
MODULE_LICENSE("GPL");
|