From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Mateusz Koza Date: Fri, 18 Jul 2025 14:49:59 +0200 Subject: Add support for Grinn GenioSBC-700 Add device tree support for the Grinn GenioSBC-700 single-board computer. This SBC is based on the Grinn GenioSOM-700 module, which integrates MediaTek's Genio 700 SoC. Hardware specifications and documentation can be found at: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/grinn-genio-700-sbc.dts | 24 + arch/arm/dts/grinn-genio-sbc.dtsi | 258 ++++++++++ arch/arm/dts/grinn-genio-som.dtsi | 98 ++++ configs/grinn_genio_700_sbc_defconfig | 140 +++++ 5 files changed, 522 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 111111111111..222222222222 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1251,7 +1251,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ genio-1200-evk-ufs-qspi.dtb \ genio-1200-radxa-nio-12l-d4.dtb \ genio-1200-radxa-nio-12l-d8.dtb \ - genio-1200-radxa-nio-12l-d16.dtb + genio-1200-radxa-nio-12l-d16.dtb \ + grinn-genio-700-sbc.dtb dtb-$(CONFIG_ARCH_NPCM7xx) += nuvoton-npcm750-evb.dtb dtb-$(CONFIG_XEN) += xenguest-arm64.dtb diff --git a/arch/arm/dts/grinn-genio-700-sbc.dts b/arch/arm/dts/grinn-genio-700-sbc.dts new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/arch/arm/dts/grinn-genio-700-sbc.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ + +/dts-v1/; + +#include + +#include "mt8188.dtsi" +#include "mt6359.dtsi" +#include "grinn-genio-som.dtsi" +#include "grinn-genio-sbc.dtsi" + +/ { + model = "Grinn GenioSBC-700"; + compatible = "grinn,genio-700-sbc", "mediatek,mt8188"; + memory@40000000 { + /* 4GB */ + device_type = "memory"; + reg = <0 0x40000000 1 0x00000000>; + }; +}; diff --git a/arch/arm/dts/grinn-genio-sbc.dtsi b/arch/arm/dts/grinn-genio-sbc.dtsi new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/arch/arm/dts/grinn-genio-sbc.dtsi @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ + +/ { + chosen { + stdout-path = &uart0; + }; + + usbhub_reset: usbhub-reset { + compatible = "regulator-fixed"; + regulator-name = "usbhub-reset"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 7 GPIO_ACTIVE_HIGH>; + enable-active-low; + }; +}; + +&uart0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&pio { + i2c0_pin: i2c0-pin { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c2_pin: i2c2-pin { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c3_pin: i2c3-pin { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c5_pin: i2c5-pin { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c6_pin: i2c6-pin { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <7>; + }; + }; + + eth_default_pins: ethdefault { + pins-cc { + pinmux = , + , + , + ; + drive-strength = ; + }; + + pins-mdio { + pinmux = , + ; + drive-strength = ; + input-enable; + }; + + pins-power { + pinmux = , + ; + output-high; + }; + + pins-rxd { + pinmux = , + , + , + ; + drive-strength = ; + }; + + pins-txd { + pinmux = , + , + , + ; + drive-strength = ; + }; + }; + + eth_sleep_pins: ethsleep { + pins-cc { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-txd { + pinmux = , + , + , + ; + }; + }; +}; + +ð { + phy-mode ="rgmii-rxid"; + phy-handle = <ðernet_phy0>; + mediatek,tx-delay-ps = <2030>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + snps,reset-active-low; + snps,reset-delays-us = <0 11000 200000>; + snps,reset-gpio = <&pio 147 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethphy0@3 { + reg = <3>; + compatible = "ethernet-phy-ieee802.3-c22"; + eee-broken-1000t; + interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&auxadc { + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&u2port0 { + status = "okay"; +}; + +&u2port1 { + status = "okay"; +}; + +&u3port1 { + status = "okay"; +}; + +&u2port2 { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&ssusb { + mediatek,force-vbus; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usbhub_reset>; + status = "okay"; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; diff --git a/arch/arm/dts/grinn-genio-som.dtsi b/arch/arm/dts/grinn-genio-som.dtsi new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/arch/arm/dts/grinn-genio-som.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ + +/ { + firmware: firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&mt6359_vufs_ldo_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; +}; + +&mt6359_vemc_1_ldo_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; +}; + +&mt6359_vusb_ldo_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; +}; + +&mmc0 { + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x1481b>; + cap-mmc-hw-reset; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&pio { + i2c1_pin: i2c1-pin { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <7>; + }; + }; +}; diff --git a/configs/grinn_genio_700_sbc_defconfig b/configs/grinn_genio_700_sbc_defconfig new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/configs/grinn_genio_700_sbc_defconfig @@ -0,0 +1,140 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="genio-700-evk" +CONFIG_COUNTER_FREQUENCY=13000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_SYS_TEXT_BASE=0x4c000000 +CONFIG_SYS_MALLOC_LEN=0x500000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="grinn-genio-700-sbc" +CONFIG_TARGET_MT8188=y +CONFIG_DEBUG_UART_BASE=0x11001100 +CONFIG_DEBUG_UART_CLOCK=26000000 +CONFIG_ARMV8_CRYPTO=y +CONFIG_SYS_LOAD_ADDR=0x4c000000 +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_DEFAULT_FDT_FILE="mediatek/mt8390-grinn-genio-700-sbc" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_LATE_INIT=y +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +CONFIG_SYS_BOOTM_LEN=0x5000000 +CONFIG_CMD_BOOTEFI_SELFTEST=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_NVEDIT_INFO=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_ADC=y +CONFIG_CMD_BIND=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MBR=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +CONFIG_CMD_BMP=y +# CONFIG_CMD_BLOCK_CACHE is not set +CONFIG_CMD_EFIDEBUG=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_ENV_IMPORT_FDT=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DEVRES=y +CONFIG_ADC_MTK=y +CONFIG_CLK=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x4d000000 +CONFIG_FASTBOOT_BUF_SIZE=0x8000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +# CONFIG_INPUT is not set +CONFIG_MISC=y +# CONFIG_MMC_QUIRKS is not set +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_MTK=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_MTK=y +CONFIG_PHY=y +CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT8188=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_CMD_PMIC=y +CONFIG_DM_PMIC=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_MT6359=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_BAUDRATE=921600 +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_MTK_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_MTU3=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d +CONFIG_USB_GADGET_PRODUCT_NUM=0x201c +CONFIG_USB_ETHER=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MEDIATEK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_SPLASH_SOURCE=y +CONFIG_BMP_24BPP=y +CONFIG_WDT=y +CONFIG_ERRNO_STR=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_IGNORE_OSINDICATIONS=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_CAPSULE_AUTHENTICATE=y +CONFIG_LMB_MAX_REGIONS=16 +CONFIG_SYSINFO=y +# CONFIG_SYSINFO_GAZERBEAM is not set +# CONFIG_SYSINFO_SANDBOX is not set +CONFIG_SYSINFO_SMBIOS=y +# CONFIG_SYSINFO_GPIO is not set -- Armbian