From be6c079fabc8012e1c89bc34d046031675da3be5 Mon Sep 17 00:00:00 2001 From: map220v Date: Wed, 15 Jan 2025 15:20:29 +0000 Subject: [PATCH] SM8550: Fix L2 cache for CPU2 and add cache sizes --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 80 +++++++++++++++++++++++++--- 1 file changed, 73 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index eac8de4005d8..f49f9ca2235a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -71,6 +71,12 @@ reg = <0 0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>; power-domain-names = "psci"; @@ -82,11 +88,17 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x20000>; + cache-line-size = <64>; + cache-sets = <256>; next-level-cache = <&l3_0>; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; + cache-size = <0x800000>; + cache-line-size = <64>; + cache-sets = <8192>; }; }; }; @@ -97,6 +109,12 @@ reg = <0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; next-level-cache = <&l2_100>; power-domains = <&cpu_pd1>; power-domain-names = "psci"; @@ -108,6 +126,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; }; @@ -118,19 +139,19 @@ reg = <0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - next-level-cache = <&l2_200>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + next-level-cache = <&l2_100>; power-domains = <&cpu_pd2>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; #cooling-cells = <2>; - l2_200: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; - }; }; cpu3: cpu@300 { @@ -139,6 +160,12 @@ reg = <0 0x300>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; next-level-cache = <&l2_300>; power-domains = <&cpu_pd3>; power-domain-names = "psci"; @@ -150,6 +177,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; next-level-cache = <&l3_0>; }; }; @@ -160,6 +190,12 @@ reg = <0 0x400>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; next-level-cache = <&l2_400>; power-domains = <&cpu_pd4>; power-domain-names = "psci"; @@ -171,6 +207,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; next-level-cache = <&l3_0>; }; }; @@ -181,6 +220,12 @@ reg = <0 0x500>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; next-level-cache = <&l2_500>; power-domains = <&cpu_pd5>; power-domain-names = "psci"; @@ -192,6 +237,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; next-level-cache = <&l3_0>; }; }; @@ -202,6 +250,12 @@ reg = <0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; next-level-cache = <&l2_600>; power-domains = <&cpu_pd6>; power-domain-names = "psci"; @@ -213,6 +267,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; next-level-cache = <&l3_0>; }; }; @@ -223,6 +280,12 @@ reg = <0 0x700>; clocks = <&cpufreq_hw 2>; enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; next-level-cache = <&l2_700>; power-domains = <&cpu_pd7>; power-domain-names = "psci"; @@ -234,6 +297,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; next-level-cache = <&l3_0>; }; };