From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 14 Mar 2021 04:52:34 +0300 Subject: drm/msm/dpu1: improve support for active CTLs - Support setting master interface if several INTFs are to be handled by a single CTL - Support setting handling several MERGE_3D instances using a single CTL. Signed-off-by: Dmitry Baryshkov [Marijn: Rebase patch on -next, fix conflicting implementation with recent MERGE_3D patch, implement proper active support for DSC] Signed-off-by: Marijn Suijten --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 38 ++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 + 2 files changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -544,10 +544,12 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, struct dpu_hw_intf_cfg *cfg) { struct dpu_hw_blk_reg_map *c = &ctx->hw; - u32 intf_active = 0; - u32 dsc_active = 0; - u32 wb_active = 0; u32 mode_sel = 0; + u32 cdm_active; + u32 intf_active; + u32 wb_active; + u32 dsc_active; + u32 merge_3d_active; /* CTL_TOP[31:28] carries group_id to collate CTL paths * per VM. Explicitly disable it until VM support is @@ -559,9 +561,14 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD) mode_sel |= BIT(17); + cdm_active = DPU_REG_READ(c, CTL_CDM_ACTIVE); intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE); + merge_3d_active = DPU_REG_READ(c, CTL_MERGE_3D_ACTIVE); + + if (cfg->cdm) + cdm_active |= cfg->cdm; if (cfg->intf) intf_active |= BIT(cfg->intf - INTF_0); @@ -572,17 +579,23 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->dsc) dsc_active |= cfg->dsc; + if (cfg->merge_3d) + merge_3d_active |= BIT(cfg->merge_3d - MERGE_3D_0); + DPU_REG_WRITE(c, CTL_TOP, mode_sel); + DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active); DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active); DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active); + DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active); - if (cfg->merge_3d) - DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, - BIT(cfg->merge_3d - MERGE_3D_0)); + if (cfg->intf_master) + DPU_REG_WRITE(c, CTL_INTF_MASTER, BIT(cfg->intf_master - INTF_0)); - if (cfg->cdm) - DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm); + if (cfg->intf_master) + DPU_DEBUG_DRIVER("ACTIVE: intf:%#x merge_3d:%#x dsc:%#x master_intf:%d\n", intf_active, merge_3d_active, dsc_active, cfg->intf_master - INTF_0); + else + DPU_DEBUG_DRIVER("ACTIVE: intf:%#x merge_3d:%#x dsc:%#x\n", intf_active, merge_3d_active, dsc_active); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, @@ -623,6 +636,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, { struct dpu_hw_blk_reg_map *c = &ctx->hw; u32 intf_active = 0; + u32 intf_master = 0; u32 wb_active = 0; u32 merge3d_active = 0; u32 dsc_active; @@ -649,6 +663,14 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); intf_active &= ~BIT(cfg->intf - INTF_0); DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); + + /* Unset this intf as master, if it is the current master */ + /* TODO: Marijn: does this make any sense? */ + intf_master = DPU_REG_READ(c, CTL_INTF_MASTER); + if (intf_master == BIT(cfg->intf - INTF_0)) { + DPU_DEBUG_DRIVER("Unsetting intf:%d master\n", cfg->intf - INTF_0); + DPU_REG_WRITE(c, CTL_INTF_MASTER, 0); + } } if (cfg->wb) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -36,6 +36,7 @@ struct dpu_hw_stage_cfg { /** * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface * @intf : Interface id + * @intf_master: Master interface id in the dual pipe topology * @mode_3d: 3d mux configuration * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid @@ -45,6 +46,7 @@ struct dpu_hw_stage_cfg { */ struct dpu_hw_intf_cfg { enum dpu_intf intf; + enum dpu_intf intf_master; enum dpu_wb wb; enum dpu_3d_blend_mode mode_3d; enum dpu_merge_3d merge_3d; -- Armbian