From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 1 Jan 2021 18:55:05 +0100 Subject: clk: meson: meson8b: Add the mpeg_rtc_osc_sel clock The first input of the CLK81 clock tree uses the SoC's external oscillators. By default it's the 24MHz XTAL from which most frequencies in this SoC are derived. For power-saving purposes there's a mux to switch the input between the 24MHz XTAL and the 32kHz RTC oscillator. Add support for that mux add it to the CLK81 clock tree for a better representation of how the hardware is actually designed. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 26 +++++++++- include/dt-bindings/clock/meson8b-clkc.h | 1 + 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 111111111111..222222222222 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -611,7 +611,24 @@ static struct clk_regmap meson8b_mpll2 = { }, }; -static u32 mux_table_clk81[] = { 6, 5, 7 }; +static struct clk_regmap meson8b_mpeg_rtc_osc_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_MPEG_CLK_CNTL, + .mask = 0x1, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpeg_rtc_osc_sel", + .ops = &clk_regmap_mux_ro_ops, + .parent_data = (const struct clk_parent_data[]) { + { .fw_name = "xtal", .index = -1, }, + { .fw_name = "rtc_32k", .index = -1, }, + }, + .num_parents = 2, + }, +}; + +static u32 mux_table_clk81[] = { 0, 6, 5, 7 }; static struct clk_regmap meson8b_mpeg_clk_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_MPEG_CLK_CNTL, @@ -628,11 +645,12 @@ static struct clk_regmap meson8b_mpeg_clk_sel = { * fclk_div4, fclk_div3, fclk_div5 */ .parent_hws = (const struct clk_hw *[]) { + &meson8b_mpeg_rtc_osc_sel.hw, &meson8b_fclk_div3.hw, &meson8b_fclk_div4.hw, &meson8b_fclk_div5.hw, }, - .num_parents = 3, + .num_parents = 4, }, }; @@ -3055,6 +3073,7 @@ static struct clk_hw *meson8_hw_clks[] = { [CLKID_ETH_CLK_DIV] = &meson8_eth_clk_div.hw, [CLKID_ETH_CLK_PHASE] = &meson8_eth_clk_phase.hw, [CLKID_ETH_CLK] = &meson8_eth_clk_gate.hw, + [CLKID_MPEG_RTC_OSC_SEL] = &meson8b_mpeg_rtc_osc_sel.hw, }; static struct clk_hw *meson8b_hw_clks[] = { @@ -3270,6 +3289,7 @@ static struct clk_hw *meson8b_hw_clks[] = { [CLKID_CTS_I958] = &meson8b_cts_i958.hw, [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, + [CLKID_MPEG_RTC_OSC_SEL] = &meson8b_mpeg_rtc_osc_sel.hw, }; static struct clk_hw *meson8m2_hw_clks[] = { @@ -3487,6 +3507,7 @@ static struct clk_hw *meson8m2_hw_clks[] = { [CLKID_CTS_I958] = &meson8b_cts_i958.hw, [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, + [CLKID_MPEG_RTC_OSC_SEL] = &meson8b_mpeg_rtc_osc_sel.hw, }; static struct clk_regmap *const meson8b_clk_regmaps[] = { @@ -3687,6 +3708,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8_eth_clk_div, &meson8_eth_clk_phase, &meson8_eth_clk_gate, + &meson8b_mpeg_rtc_osc_sel, }; static const struct meson8b_clk_reset_line { diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 111111111111..222222222222 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -225,5 +225,6 @@ #define CLKID_ETH_CLK_DIV 219 #define CLKID_ETH_CLK_PHASE 220 #define CLKID_ETH_CLK 221 +#define CLKID_MPEG_RTC_OSC_SEL 222 #endif /* __MESON8B_CLKC_H */ -- Armbian