/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2010 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. */ #ifndef _DW_ETH_H #define _DW_ETH_H #ifdef CONFIG_DM_GPIO #include #endif #ifdef CONFIG_DM_ETH #include #include #endif #define CONFIG_TX_DESCR_NUM 16 #define CONFIG_RX_DESCR_NUM 16 #define CONFIG_ETH_BUFSIZE 2048 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) struct eth_mac_regs { u32 conf; /* 0x00 */ u32 framefilt; /* 0x04 */ u32 hashtablehigh; /* 0x08 */ u32 hashtablelow; /* 0x0c */ u32 miiaddr; /* 0x10 */ u32 miidata; /* 0x14 */ u32 flowcontrol; /* 0x18 */ u32 vlantag; /* 0x1c */ u32 version; /* 0x20 */ u8 reserved_1[20]; u32 intreg; /* 0x38 */ u32 intmask; /* 0x3c */ u32 macaddr0hi; /* 0x40 */ u32 macaddr0lo; /* 0x44 */ }; /* MAC configuration register definitions */ #define FRAMEBURSTENABLE (1 << 21) #define MII_PORTSELECT (1 << 15) #define FES_100 (1 << 14) #define DISABLERXOWN (1 << 13) #define FULLDPLXMODE (1 << 11) #define RXENABLE (1 << 2) #define TXENABLE (1 << 3) /* MII address register definitions */ #define MII_BUSY (1 << 0) #define MII_WRITE (1 << 1) #define MII_CLKRANGE_60_100M (0) #define MII_CLKRANGE_100_150M (0x4) #define MII_CLKRANGE_20_35M (0x8) #define MII_CLKRANGE_35_60M (0xC) #define MII_CLKRANGE_150_250M (0x10) #define MII_CLKRANGE_250_300M (0x14) #define MIIADDRSHIFT (11) #define MIIREGSHIFT (6) #define MII_REGMSK (0x1F << 6) #define MII_ADDRMSK (0x1F << 11) struct eth_dma_regs { u32 busmode; /* 0x00 */ u32 txpolldemand; /* 0x04 */ u32 rxpolldemand; /* 0x08 */ u32 rxdesclistaddr; /* 0x0c */ u32 txdesclistaddr; /* 0x10 */ u32 status; /* 0x14 */ u32 opmode; /* 0x18 */ u32 intenable; /* 0x1c */ u32 reserved1[2]; u32 axibus; /* 0x28 */ u32 reserved2[7]; u32 currhosttxdesc; /* 0x48 */ u32 currhostrxdesc; /* 0x4c */ u32 currhosttxbuffaddr; /* 0x50 */ u32 currhostrxbuffaddr; /* 0x54 */ }; #define DW_DMA_BASE_OFFSET (0x1000) /* Default DMA Burst length */ #ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 #endif /* Bus mode register definitions */ #define FIXEDBURST (1 << 16) #define PRIORXTX_41 (3 << 14) #define PRIORXTX_31 (2 << 14) #define PRIORXTX_21 (1 << 14) #define PRIORXTX_11 (0 << 14) #define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) #define RXHIGHPRIO (1 << 1) #define DMAMAC_SRST (1 << 0) /* Poll demand definitions */ #define POLL_DATA (0xFFFFFFFF) /* Operation mode definitions */ #define STOREFORWARD (1 << 21) #define FLUSHTXFIFO (1 << 20) #define TXSTART (1 << 13) #define TXSECONDFRAME (1 << 2) #define RXSTART (1 << 1) /* Descriptior related definitions */ #define MAC_MAX_FRAME_SZ (1600) struct dmamacdescr { u32 txrx_status; u32 dmamac_cntl; u32 dmamac_addr; u32 dmamac_next; } __aligned(ARCH_DMA_MINALIGN); /* * txrx_status definitions */ /* tx status bits definitions */ #if defined(CONFIG_DW_ALTDESCRIPTOR) #define DESC_TXSTS_OWNBYDMA (1 << 31) #define DESC_TXSTS_TXINT (1 << 30) #define DESC_TXSTS_TXLAST (1 << 29) #define DESC_TXSTS_TXFIRST (1 << 28) #define DESC_TXSTS_TXCRCDIS (1 << 27) #define DESC_TXSTS_TXPADDIS (1 << 26) #define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) #define DESC_TXSTS_TXRINGEND (1 << 21) #define DESC_TXSTS_TXCHAIN (1 << 20) #define DESC_TXSTS_MSK (0x1FFFF << 0) #else #define DESC_TXSTS_OWNBYDMA (1 << 31) #define DESC_TXSTS_MSK (0x1FFFF << 0) #endif /* rx status bits definitions */ #define DESC_RXSTS_OWNBYDMA (1 << 31) #define DESC_RXSTS_DAFILTERFAIL (1 << 30) #define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) #define DESC_RXSTS_FRMLENSHFT (16) #define DESC_RXSTS_ERROR (1 << 15) #define DESC_RXSTS_RXTRUNCATED (1 << 14) #define DESC_RXSTS_SAFILTERFAIL (1 << 13) #define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) #define DESC_RXSTS_RXDAMAGED (1 << 11) #define DESC_RXSTS_RXVLANTAG (1 << 10) #define DESC_RXSTS_RXFIRST (1 << 9) #define DESC_RXSTS_RXLAST (1 << 8) #define DESC_RXSTS_RXIPC_GIANT (1 << 7) #define DESC_RXSTS_RXCOLLISION (1 << 6) #define DESC_RXSTS_RXFRAMEETHER (1 << 5) #define DESC_RXSTS_RXWATCHDOG (1 << 4) #define DESC_RXSTS_RXMIIERROR (1 << 3) #define DESC_RXSTS_RXDRIBBLING (1 << 2) #define DESC_RXSTS_RXCRC (1 << 1) /* * dmamac_cntl definitions */ /* tx control bits definitions */ #if defined(CONFIG_DW_ALTDESCRIPTOR) #define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0) #define DESC_TXCTRL_SIZE1SHFT (0) #define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16) #define DESC_TXCTRL_SIZE2SHFT (16) #else #define DESC_TXCTRL_TXINT (1 << 31) #define DESC_TXCTRL_TXLAST (1 << 30) #define DESC_TXCTRL_TXFIRST (1 << 29) #define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) #define DESC_TXCTRL_TXCRCDIS (1 << 26) #define DESC_TXCTRL_TXRINGEND (1 << 25) #define DESC_TXCTRL_TXCHAIN (1 << 24) #define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) #define DESC_TXCTRL_SIZE1SHFT (0) #define DESC_TXCTRL_SIZE2MASK (0x7FF << 11) #define DESC_TXCTRL_SIZE2SHFT (11) #endif /* rx control bits definitions */ #if defined(CONFIG_DW_ALTDESCRIPTOR) #define DESC_RXCTRL_RXINTDIS (1 << 31) #define DESC_RXCTRL_RXRINGEND (1 << 15) #define DESC_RXCTRL_RXCHAIN (1 << 14) #define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) #define DESC_RXCTRL_SIZE1SHFT (0) #define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16) #define DESC_RXCTRL_SIZE2SHFT (16) #else #define DESC_RXCTRL_RXINTDIS (1 << 31) #define DESC_RXCTRL_RXRINGEND (1 << 25) #define DESC_RXCTRL_RXCHAIN (1 << 24) #define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) #define DESC_RXCTRL_SIZE1SHFT (0) #define DESC_RXCTRL_SIZE2MASK (0x7FF << 11) #define DESC_RXCTRL_SIZE2SHFT (11) #endif struct dw_eth_dev { struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); u32 interface; u32 max_speed; u32 tx_currdescnum; u32 rx_currdescnum; struct eth_mac_regs *mac_regs_p; struct eth_dma_regs *dma_regs_p; #ifndef CONFIG_DM_ETH struct eth_device *dev; #endif #ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; #endif #ifdef CONFIG_CLK struct clk *clocks; /* clock list */ int clock_count; /* number of clock in clock list */ #endif struct phy_device *phydev; struct mii_dev *bus; }; #ifdef CONFIG_DM_ETH int designware_eth_ofdata_to_platdata(struct udevice *dev); int designware_eth_probe(struct udevice *dev); extern const struct eth_ops designware_eth_ops; struct dw_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; }; int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr); int designware_eth_enable(struct dw_eth_dev *priv); int designware_eth_send(struct udevice *dev, void *packet, int length); int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp); int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length); void designware_eth_stop(struct udevice *dev); int designware_eth_write_hwaddr(struct udevice *dev); #endif struct eqos_mac_regs { uint32_t configuration; /* 0x000 */ uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */ uint32_t q0_tx_flow_ctrl; /* 0x070 */ uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ uint32_t rx_flow_ctrl; /* 0x090 */ uint32_t unused_094; /* 0x094 */ uint32_t txq_prty_map0; /* 0x098 */ uint32_t unused_09c; /* 0x09c */ uint32_t rxq_ctrl0; /* 0x0a0 */ uint32_t unused_0a4; /* 0x0a4 */ uint32_t rxq_ctrl2; /* 0x0a8 */ uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ uint32_t us_tic_counter; /* 0x0dc */ uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ uint32_t hw_feature0; /* 0x11c */ uint32_t hw_feature1; /* 0x120 */ uint32_t hw_feature2; /* 0x124 */ uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */ uint32_t mdio_address; /* 0x200 */ uint32_t mdio_data; /* 0x204 */ uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */ uint32_t address0_high; /* 0x300 */ uint32_t address0_low; /* 0x304 */ }; #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23) #define EQOS_MAC_CONFIGURATION_CST BIT(21) #define EQOS_MAC_CONFIGURATION_ACS BIT(20) #define EQOS_MAC_CONFIGURATION_WD BIT(19) #define EQOS_MAC_CONFIGURATION_JD BIT(17) #define EQOS_MAC_CONFIGURATION_JE BIT(16) #define EQOS_MAC_CONFIGURATION_PS BIT(15) #define EQOS_MAC_CONFIGURATION_FES BIT(14) #define EQOS_MAC_CONFIGURATION_DM BIT(13) #define EQOS_MAC_CONFIGURATION_TE BIT(1) #define EQOS_MAC_CONFIGURATION_RE BIT(0) #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0) #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 #define EQOS_MAC_MDIO_ADDRESS_CR_150_250 4 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) #define EQOS_MAC_MDIO_ADDRESS_GB 1 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff #define EQOS_MTL_REGS_BASE 0xd00 struct eqos_mtl_regs { uint32_t txq0_operation_mode; /* 0xd00 */ uint32_t unused_d04; /* 0xd04 */ uint32_t txq0_debug; /* 0xd08 */ uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */ uint32_t txq0_quantum_weight; /* 0xd18 */ uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */ uint32_t rxq0_operation_mode; /* 0xd30 */ uint32_t unused_d34; /* 0xd34 */ uint32_t rxq0_debug; /* 0xd38 */ //uint32_t rxq0_cntl; /* 0xd3C */ }; #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4) #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3 #define EQOS_DMA_REGS_BASE 0x1000 struct eqos_dma_regs { uint32_t mode; /* 0x1000 */ uint32_t sysbus_mode; /* 0x1004 */ uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */ uint32_t ch0_control; /* 0x1100 */ uint32_t ch0_tx_control; /* 0x1104 */ uint32_t ch0_rx_control; /* 0x1108 */ uint32_t unused_110c; /* 0x110c */ uint32_t ch0_txdesc_list_haddress; /* 0x1110 */ uint32_t ch0_txdesc_list_address; /* 0x1114 */ uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */ uint32_t ch0_rxdesc_list_address; /* 0x111c */ uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */ uint32_t unused_1124; /* 0x1124 */ uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */ uint32_t ch0_txdesc_ring_length; /* 0x112c */ uint32_t ch0_rxdesc_ring_length; /* 0x1130 */ }; #define EQOS_DMA_MODE_SWR BIT(0) #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11) #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3) #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2) #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1) #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16) #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4) #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0) #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0) /* Descriptors */ #define EQOS_DESCRIPTOR_WORDS 4 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4) /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */ #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN #define EQOS_DESCRIPTORS_TX 4 #define EQOS_DESCRIPTORS_RX 4 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX) #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \ EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN) #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE) struct eqos_desc { u32 des0; u32 des1; u32 des2; u32 des3; }; #define EQOS_DESC3_OWN BIT(31) #define EQOS_DESC3_FD BIT(29) #define EQOS_DESC3_LD BIT(28) #define EQOS_DESC3_BUF1V BIT(24) struct eqos_eth_dev { struct udevice *dev; struct eqos_mac_regs *mac_regs_p; struct eqos_mtl_regs *mtl_regs_p; struct eqos_dma_regs *dma_regs_p; struct mii_dev *bus; struct phy_device *phydev; u32 interface; void *descs; struct eqos_desc *tx_descs; struct eqos_desc *rx_descs; int tx_desc_idx, rx_desc_idx; void *tx_dma_buf; void *rx_dma_buf; void *rx_pkt; }; #ifdef CONFIG_DM_ETH struct aml_phy_dev { void __iomem *phy_top; void __iomem *phy_cfg; struct dev_pm_ops *pm_ops; }; int aml_phy_suspend(void *pm_ops); int aml_phy_resume(void *pm_ops); int aml_phy_poweroff(void *pm_ops); #endif #endif