/* * Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved. * * SPDX-License-Identifier: MIT */ #ifndef _ETH_PHY_H__ #define _ETH_PHY_H__ #include #include #include #if defined(CONFIG_ETHERNET_CFG) #include #endif /* CONFIG_ETHERNET_CFG */ #ifdef __cplusplus extern "C" { #endif #if !defined(ETH_PHY_ADDR) #if defined(CONFIG_ETHERNET_INTERNAL_PHY) #define ETH_PHY_ADDR 0x08 #elif defined(CONFIG_ETHERNET_EXTERNAL_PHY) #define ETH_PHY_ADDR 0x01 #endif #endif /* Basic Control Register */ #define EPHY_BMCR 0x00 #define EPHY_BMCR_RESET BIT(15) #define EPHY_BMCR_PDOWN BIT(11) /* Basic Status Register */ #define EPHY_BMSR 0x01 #define EPHY_BMSR_LSTATUS BIT(2) /* PHY Identifier */ #define EPHY_ID1 0x02 #define EPHY_ID2 0x03 int xPhyReadId(uint32_t *phyId); int xPhyReadLinkStatus(bool *status); void vPhyInit(void); void vPhyDeinit(void); #ifdef __cplusplus } #endif #endif /* _ETH_PHY_H__ */