/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
 */

#define PDID_S5_MALI_0		0
#define PDID_S5_MALI_1		1
#define PDID_S5_MALI_2		2
#define PDID_S5_MALI_TOP	3
#define PDID_S5_DOS_TOP_WRAP	4
#define PDID_S5_DOS_VDEC	5
#define PDID_S5_DOS_HCODEC	6
#define PDID_S5_DOS_HEVC_TOP	7
#define PDID_S5_DOS_HEVC_CORE1	8
#define PDID_S5_USB2		9
#define PDID_S5_PCIE0		10
#define PDID_S5_GE2D		11
#define PDID_S5_VC9000E		12
#define PDID_S5_VICP		13
#define PDID_S5_VGE_TOP		14
#define PDID_S5_VI_CLK1		15
#define PDID_S5_VI_CLK2		16
#define PDID_S5_VPU_HDMI	17
#define PDID_S5_ETH		18
#define PDID_S5_PCIE1		19
#define PDID_S5_VPU_DOLBY	20
#define PDID_S5_USB30		21
#define PDID_S5_USB31		22
#define PDID_S5_SDCARD		23
#define PDID_S5_SDIO		24
#define PDID_S5_NAND_EMMC	25
#define PDID_S5_NNA_4T		26
#define PDID_S5_DMC00		27
#define PDID_S5_DMC01		28
#define PDID_S5_NOC_DMC_TOP	29
#define PDID_S5_DMC10		30
#define PDID_S5_DMC11		31
#define PDID_S5_DDRPHY0		32
#define PDID_S5_DDRPHY1		33