/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#define PDID_C5_USB2		0
#define PDID_C5_USB3		1
#define PDID_C5_DOS_HCODEC		2
#define PDID_C5_DOS_HEVC			3
#define PDID_C5_TAHOE		4
#define PDID_C5_VPU_VOUT		5
#define PDID_C5_SD_EMMC_A		6
#define PDID_C5_SD_EMMC_B		7
#define PDID_C5_SD_EMMC_C			8
#define PDID_C5_ETH		9
#define PDID_C5_NNA3		10
#define PDID_C5_NNA2		11
#define PDID_C5_AMFC		12
#define PDID_C5_ISP			13
#define PDID_C5_GE2D		14
#define PDID_C5_CVE		15
#define PDID_C5_DEWARP		16
#define PDID_C5_AI_ISP		17
#define PDID_C5_DSI			18
#define PDID_C5_PCIE		19
#define PDID_C5_U3P2_COMP   20
#define PDID_C5_AO_SED		21
#define PDID_C5_AO_ISP		22
#define PDID_C5_AO_SPI		23
#define PDID_C5_AO_UART_A			24
#define PDID_C5_AO_UART_B		25
#define PDID_C5_AO_SPISG		26
#define PDID_C5_AO_I2C_A		27
#define PDID_C5_AO_I2C_B		28
#define PDID_C5_AO_I3C			29
#define PDID_C5_AO_IR		30
#define PDID_C5_AO_PWM_A		31
#define PDID_C5_AO_PWM_B		32
#define PDID_C5_AO_PSRAM		33
#define PDID_C5_AUDIO_TOP		34
#define PDID_C5_CAN0                    35
#define PDID_C5_CAN1                    36