/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2019 Amlogic, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S7_CLKC_H #define _DT_BINDINGS_CLOCK_AMLOGIC_S7_CLKC_H #define CLKID_FIXED_PLL 0 #define CLKID_GP0_PLL 1 #define CLKID_HIFI_PLL 2 #define CLKID_HIFI1_PLL 3 #define CLKID_FCLK_50M_DIV 4 #define CLKID_FCLK_50M 5 #define CLKID_FCLK_DIV2_DIV 6 #define CLKID_FCLK_DIV2 7 #define CLKID_FCLK_DIV2P5_DIV 8 #define CLKID_FCLK_DIV2P5 9 #define CLKID_FCLK_DIV3_DIV 10 #define CLKID_FCLK_DIV3 11 #define CLKID_FCLK_DIV4_DIV 12 #define CLKID_FCLK_DIV4 13 #define CLKID_FCLK_DIV5_DIV 14 #define CLKID_FCLK_DIV5 15 #define CLKID_FCLK_DIV7_DIV 16 #define CLKID_FCLK_DIV7 17 #define CLKID_SYS_CLK_0_MUX 18 #define CLKID_SYS_CLK_0_DIV 19 #define CLKID_SYS_CLK_0 20 #define CLKID_SYS_CLK_1_MUX 21 #define CLKID_SYS_CLK_1_DIV 22 #define CLKID_SYS_CLK_1 23 #define CLKID_SYS_CLK 24 #define CLKID_AXI_CLK_0_MUX 25 #define CLKID_AXI_CLK_0_DIV 26 #define CLKID_AXI_CLK_0 27 #define CLKID_AXI_CLK_1_MUX 28 #define CLKID_AXI_CLK_1_DIV 29 #define CLKID_AXI_CLK_1 30 #define CLKID_AXI_CLK 31 #define CLKID_RTC_DUAL_CLKIN 32 #define CLKID_RTC_DUAL_DIV 33 #define CLKID_RTC_DUAL_MUX 34 #define CLKID_RTC_DUAL 35 #define CLKID_RTC_CLK 36 #define CLKID_SAR_ADC_MUX 37 #define CLKID_SAR_ADC_DIV 38 #define CLKID_SAR_ADC 39 #define CLKID_CECB_DUAL_CLKIN 40 #define CLKID_CECB_DUAL_DIV 41 #define CLKID_CECB_DUAL_MUX 42 #define CLKID_CECB_DUAL 43 #define CLKID_CECB_CLK 44 #define CLKID_SC_MUX 45 #define CLKID_SC_DIV 46 #define CLKID_SC 47 #define CLKID_CDAC_MUX 48 #define CLKID_CDAC_DIV 49 #define CLKID_CDAC 50 #define CLKID_VIDEO_SRC0_IN_MUX 51 #define CLKID_VIDEO_SRC0_IN 52 #define CLKID_VIDEO_SRC0_DIV 53 #define CLKID_VIDEO_SRC0 54 #define CLKID_VIDEO_SRC1_IN_MUX 55 #define CLKID_VIDEO_SRC1_IN 56 #define CLKID_VIDEO_SRC1_DIV 57 #define CLKID_VIDEO_SRC1 58 #define CLKID_VIDEO0_DIV1 59 #define CLKID_VIDEO0_DIV2_GATE 60 #define CLKID_VIDEO0_DIV2 61 #define CLKID_VIDEO0_DIV4_GATE 62 #define CLKID_VIDEO0_DIV4 63 #define CLKID_VIDEO0_DIV6_GATE 64 #define CLKID_VIDEO0_DIV6 65 #define CLKID_VIDEO0_DIV12_GATE 66 #define CLKID_VIDEO0_DIV12 67 #define CLKID_VIDEO1_DIV1 68 #define CLKID_VIDEO1_DIV2_GATE 69 #define CLKID_VIDEO1_DIV2 70 #define CLKID_VIDEO1_DIV4_GATE 71 #define CLKID_VIDEO1_DIV4 72 #define CLKID_VIDEO1_DIV6_GATE 73 #define CLKID_VIDEO1_DIV6 74 #define CLKID_VIDEO1_DIV12_GATE 75 #define CLKID_VIDEO1_DIV12 76 #define CLKID_LCD_AN_MUX 77 #define CLKID_LCD_AN 78 #define CLKID_LCD_AN_PH2 79 #define CLKID_LCD_AN_PH3 80 #define CLKID_ENCI_MUX 81 #define CLKID_ENCI 82 #define CLKID_ENCP_MUX 83 #define CLKID_ENCP 84 #define CLKID_ENCL_MUX 85 #define CLKID_ENCL 86 #define CLKID_VDAC_MUX 87 #define CLKID_VDAC 88 #define CLKID_HDMITX_PIXEL_MUX 89 #define CLKID_HDMITX_PIXEL 90 #define CLKID_HDMITX_FE_MUX 91 #define CLKID_HDMITX_FE 92 #define CLKID_MALI_0_MUX 93 #define CLKID_MALI_0_DIV 94 #define CLKID_MALI_0 95 #define CLKID_MALI_1_MUX 96 #define CLKID_MALI_1_DIV 97 #define CLKID_MALI_1 98 #define CLKID_MALI 99 #define CLKID_VDEC_0_MUX 100 #define CLKID_VDEC_0_DIV 101 #define CLKID_VDEC_0 102 #define CLKID_VDEC_1_MUX 103 #define CLKID_VDEC_1_DIV 104 #define CLKID_VDEC_1 105 #define CLKID_VDEC 106 #define CLKID_HEVCF_0_MUX 107 #define CLKID_HEVCF_0_DIV 108 #define CLKID_HEVCF_0 109 #define CLKID_HEVCF_1_MUX 110 #define CLKID_HEVCF_1_DIV 111 #define CLKID_HEVCF_1 112 #define CLKID_HEVCF 113 #define CLKID_HCODEC_0_MUX 114 #define CLKID_HCODEC_0_DIV 115 #define CLKID_HCODEC_0 116 #define CLKID_HCODEC_1_MUX 117 #define CLKID_HCODEC_1_DIV 118 #define CLKID_HCODEC_1 119 #define CLKID_HCODEC 120 #define CLKID_VPU_0_MUX 121 #define CLKID_VPU_0_DIV 122 #define CLKID_VPU_0 123 #define CLKID_VPU_1_MUX 124 #define CLKID_VPU_1_DIV 125 #define CLKID_VPU_1 126 #define CLKID_VPU 127 #define CLKID_VPU_CLKB_TMP_MUX 128 #define CLKID_VPU_CLKB_TMP_DIV 129 #define CLKID_VPU_CLKB_TMP 130 #define CLKID_VPU_CLKB_DIV 131 #define CLKID_VPU_CLKB 132 #define CLKID_VPU_CLKC_0_MUX 133 #define CLKID_VPU_CLKC_0_DIV 134 #define CLKID_VPU_CLKC_0 135 #define CLKID_VPU_CLKC_1_MUX 136 #define CLKID_VPU_CLKC_1_DIV 137 #define CLKID_VPU_CLKC_1 138 #define CLKID_VPU_CLKC 139 #define CLKID_VAPB_0_MUX 140 #define CLKID_VAPB_0_DIV 141 #define CLKID_VAPB_0 142 #define CLKID_VAPB_1_MUX 143 #define CLKID_VAPB_1_DIV 144 #define CLKID_VAPB_1 145 #define CLKID_VAPB 146 #define CLKID_GE2D 147 #define CLKID_HDMITX_SYS_MUX 148 #define CLKID_HDMITX_SYS_DIV 149 #define CLKID_HDMITX_SYS 150 #define CLKID_HDMITX_PRIF_MUX 151 #define CLKID_HDMITX_PRIF_DIV 152 #define CLKID_HDMITX_PRIF 153 #define CLKID_HDMITX_200M_MUX 154 #define CLKID_HDMITX_200M_DIV 155 #define CLKID_HDMITX_200M 156 #define CLKID_HDMITX_AUD_MUX 157 #define CLKID_HDMITX_AUD_DIV 158 #define CLKID_HDMITX_AUD 159 #define CLKID_PWM_A_MUX 160 #define CLKID_PWM_A_DIV 161 #define CLKID_PWM_A 162 #define CLKID_PWM_B_MUX 163 #define CLKID_PWM_B_DIV 164 #define CLKID_PWM_B 165 #define CLKID_PWM_C_MUX 166 #define CLKID_PWM_C_DIV 167 #define CLKID_PWM_C 168 #define CLKID_PWM_D_MUX 169 #define CLKID_PWM_D_DIV 170 #define CLKID_PWM_D 171 #define CLKID_PWM_E_MUX 172 #define CLKID_PWM_E_DIV 173 #define CLKID_PWM_E 174 #define CLKID_PWM_F_MUX 175 #define CLKID_PWM_F_DIV 176 #define CLKID_PWM_F 177 #define CLKID_SPICC0_MUX 178 #define CLKID_SPICC0_DIV 179 #define CLKID_SPICC0 180 #define CLKID_SD_EMMC_A_MUX 181 #define CLKID_SD_EMMC_A_DIV 182 #define CLKID_SD_EMMC_A 183 #define CLKID_SD_EMMC_B_MUX 184 #define CLKID_SD_EMMC_B_DIV 185 #define CLKID_SD_EMMC_B 186 #define CLKID_SD_EMMC_C_MUX 187 #define CLKID_SD_EMMC_C_DIV 188 #define CLKID_SD_EMMC_C 189 #define CLKID_VDIN_MEAS_MUX 190 #define CLKID_VDIN_MEAS_DIV 191 #define CLKID_VDIN_MEAS 192 #define CLKID_VID_LOCK_MUX 193 #define CLKID_VID_LOCK_DIV 194 #define CLKID_VID_LOCK 195 #define CLKID_ETH_RMII_DIV 196 #define CLKID_ETH_RMII 197 #define CLKID_ETH_125M_DIV 198 #define CLKID_ETH_125M 199 #define CLKID_TS_DIV 200 #define CLKID_TS 201 #define CLKID_CLK_24M_IN 202 #define CLKID_CLK_12M_DIV 203 #define CLKID_CLK_12_24M 204 #define CLKID_GEN_MUX 205 #define CLKID_GEN_DIV 206 #define CLKID_GEN 207 #define CLKID_SYS_AM_AXI 208 #define CLKID_SYS_DOS 209 #define CLKID_SYS_ETHPHY 210 #define CLKID_SYS_MALI 211 #define CLKID_SYS_AOCPU 212 #define CLKID_SYS_AUCPU 213 #define CLKID_SYS_CEC 214 #define CLKID_SYS_SD_EMMC_A 215 #define CLKID_SYS_SD_EMMC_B 216 #define CLKID_SYS_SD_EMMC_C 217 #define CLKID_SYS_SMARTCARD 218 #define CLKID_SYS_ACODEC 219 #define CLKID_SYS_MSR_CLK 220 #define CLKID_SYS_IR_CTRL 221 #define CLKID_SYS_AUDIO 222 #define CLKID_SYS_ETH 223 #define CLKID_SYS_UART_A 224 #define CLKID_SYS_UART_B 225 #define CLKID_SYS_UART_C 226 #define CLKID_SYS_UART_D 227 #define CLKID_SYS_UART_E 228 #define CLKID_SYS_TS_PLL 229 #define CLKID_SYS_GE2D 230 #define CLKID_SYS_SPICC0 231 #define CLKID_SYS_USB 232 #define CLKID_SYS_I2C_M_A 233 #define CLKID_SYS_I2C_M_B 234 #define CLKID_SYS_I2C_M_C 235 #define CLKID_SYS_I2C_M_D 236 #define CLKID_SYS_I2C_M_E 237 #define CLKID_SYS_HDMITX_APB 238 #define CLKID_SYS_I2C_S_A 239 #define CLKID_SYS_HDMI20_AES 240 #define CLKID_SYS_MMC_APB 241 #define CLKID_SYS_CPU_APB 242 #define CLKID_SYS_VPU_INTR 243 #define CLKID_SYS_SAR_ADC 244 #define CLKID_SYS_PWM_J 245 #define CLKID_SYS_GIC 246 #define CLKID_SYS_PWM_I 247 #define CLKID_SYS_PWM_H 248 #define CLKID_SYS_PWM_G 249 #define CLKID_SYS_PWM_F 250 #define CLKID_SYS_PWM_E 251 #define CLKID_SYS_PWM_D 252 #define CLKID_SYS_PWM_C 253 #define CLKID_SYS_PWM_B 254 #define CLKID_SYS_PWM_A 255 #define CLKID_AXI_SYS_NIC 256 #define CLKID_AXI_RAMA 257 #define CLKID_AXI_DEV0_MMC 258 #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S7_CLKC_H */