/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S6_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_S6_CLKC_H

#define CLKID_GP0_PLL                             0
#define CLKID_HIFI_PLL                            1
#define CLKID_HIFI1_PLL                           2
#define CLKID_MCLK_PLL                            3
#define CLKID_MCLK_PLL_CLK                        4
#define CLKID_MCLK0_DIV                           5
#define CLKID_MCLK0_DIV2                          6
#define CLKID_MCLK0                               7
#define CLKID_FCLK50M_DIV                         8
#define CLKID_FCLK50M                             9
#define CLKID_FCLK_DIV2_DIV                       10
#define CLKID_FCLK_DIV2                           11
#define CLKID_FCLK_DIV2P5_DIV                     12
#define CLKID_FCLK_DIV2P5                         13
#define CLKID_FCLK_DIV3_DIV                       14
#define CLKID_FCLK_DIV3                           15
#define CLKID_FCLK_DIV4_DIV                       16
#define CLKID_FCLK_DIV4                           17
#define CLKID_FCLK_DIV5_DIV                       18
#define CLKID_FCLK_DIV5                           19
#define CLKID_FCLK_DIV7_DIV                       20
#define CLKID_FCLK_DIV7                           21
#define CLKID_RTC_DUAL_CLKIN                      22
#define CLKID_RTC_DUAL_DIV                        23
#define CLKID_RTC_DUAL_MUX                        24
#define CLKID_RTC_DUAL                            25
#define CLKID_RTC_CLK                             26
#define CLKID_CLK_24M_IN                          27
#define CLKID_CLK_12M_DIV                         28
#define CLKID_CLK_12M                             29
#define CLKID_SAR_ADC_MUX                         30
#define CLKID_SAR_ADC_DIV                         31
#define CLKID_SAR_ADC                             32
#define CLKID_CECB_DUAL_CLKIN                     33
#define CLKID_CECB_DUAL_DIV                       34
#define CLKID_CECB_DUAL_MUX                       35
#define CLKID_CECB_DUAL                           36
#define CLKID_CECB_CLK                            37
#define CLKID_SC_PRE_MUX                          38
#define CLKID_SC_PRE_DIV                          39
#define CLKID_SC_PRE                              40
#define CLKID_SC                                  41
#define CLKID_CDAC_MUX                            42
#define CLKID_CDAC_DIV                            43
#define CLKID_CDAC                                44
#define CLKID_VIDEO_SRC0_IN_MUX                   45
#define CLKID_VIDEO_SRC0_IN                       46
#define CLKID_VIDEO_SRC0_DIV                      47
#define CLKID_VIDEO_SRC0                          48
#define CLKID_VIDEO_SRC1_IN_MUX                   49
#define CLKID_VIDEO_SRC1_IN                       50
#define CLKID_VIDEO_SRC1_DIV                      51
#define CLKID_VIDEO_SRC1                          52
#define CLKID_VIDEO0_DIV1                         53
#define CLKID_VIDEO0_DIV2_GATE                    54
#define CLKID_VIDEO0_DIV2                         55
#define CLKID_VIDEO0_DIV4_GATE                    56
#define CLKID_VIDEO0_DIV4                         57
#define CLKID_VIDEO0_DIV6_GATE                    58
#define CLKID_VIDEO0_DIV6                         59
#define CLKID_VIDEO0_DIV12_GATE                   60
#define CLKID_VIDEO0_DIV12                        61
#define CLKID_VIDEO2_DIV1                         62
#define CLKID_VIDEO2_DIV2_GATE                    63
#define CLKID_VIDEO2_DIV2                         64
#define CLKID_VIDEO2_DIV4_GATE                    65
#define CLKID_VIDEO2_DIV4                         66
#define CLKID_VIDEO2_DIV6_GATE                    67
#define CLKID_VIDEO2_DIV6                         68
#define CLKID_VIDEO2_DIV12_GATE                   69
#define CLKID_VIDEO2_DIV12                        70
#define CLKID_LCD_AN_MUX                          71
#define CLKID_LCD_AN                              72
#define CLKID_LCD_AN_PH2                          73
#define CLKID_LCD_AN_PH3                          74
#define CLKID_ENCI_MUX                            75
#define CLKID_ENCI                                76
#define CLKID_ENCP_MUX                            77
#define CLKID_ENCP                                78
#define CLKID_ENCL_MUX                            79
#define CLKID_ENCL                                80
#define CLKID_VDAC_MUX                            81
#define CLKID_VDAC                                82
#define CLKID_HDMITX_PIXEL_MUX                    83
#define CLKID_HDMITX_PIXEL                        84
#define CLKID_HDMITX_FE_MUX                       85
#define CLKID_HDMITX_FE                           86
#define CLKID_MALI_0_MUX                          87
#define CLKID_MALI_0_DIV                          88
#define CLKID_MALI_0                              89
#define CLKID_MALI_1_MUX                          90
#define CLKID_MALI_1_DIV                          91
#define CLKID_MALI_1                              92
#define CLKID_MALI                                93
#define CLKID_MALI_STACK_0_MUX                    94
#define CLKID_MALI_STACK_0_DIV                    95
#define CLKID_MALI_STACK_0                        96
#define CLKID_MALI_STACK_1_MUX                    97
#define CLKID_MALI_STACK_1_DIV                    98
#define CLKID_MALI_STACK_1                        99
#define CLKID_MALI_STACK                          100
#define CLKID_VDEC_0_MUX                          101
#define CLKID_VDEC_0_DIV                          102
#define CLKID_VDEC_0                              103
#define CLKID_VDEC_1_MUX                          104
#define CLKID_VDEC_1_DIV                          105
#define CLKID_VDEC_1                              106
#define CLKID_VDEC                                107
#define CLKID_HEVCF_0_MUX                         108
#define CLKID_HEVCF_0_DIV                         109
#define CLKID_HEVCF_0                             110
#define CLKID_HEVCF_1_MUX                         111
#define CLKID_HEVCF_1_DIV                         112
#define CLKID_HEVCF_1                             113
#define CLKID_HEVCF                               114
#define CLKID_VPU_0_MUX                           115
#define CLKID_VPU_0_DIV                           116
#define CLKID_VPU_0                               117
#define CLKID_VPU_1_MUX                           118
#define CLKID_VPU_1_DIV                           119
#define CLKID_VPU_1                               120
#define CLKID_VPU                                 121
#define CLKID_VPU_CLKB_TMP_MUX                    122
#define CLKID_VPU_CLKB_TMP_DIV                    123
#define CLKID_VPU_CLKB_TMP                        124
#define CLKID_VPU_CLKB_DIV                        125
#define CLKID_VPU_CLKB                            126
#define CLKID_VPU_CLKC_0_MUX                      127
#define CLKID_VPU_CLKC_0_DIV                      128
#define CLKID_VPU_CLKC_0                          129
#define CLKID_VPU_CLKC_1_MUX                      130
#define CLKID_VPU_CLKC_1_DIV                      131
#define CLKID_VPU_CLKC_1                          132
#define CLKID_VPU_CLKC                            133
#define CLKID_VAPB_0_MUX                          134
#define CLKID_VAPB_0_DIV                          135
#define CLKID_VAPB_0                              136
#define CLKID_VAPB_1_MUX                          137
#define CLKID_VAPB_1_DIV                          138
#define CLKID_VAPB_1                              139
#define CLKID_VAPB                                140
#define CLKID_GE2D                                141
#define CLKID_DEWARPA_MUX                         142
#define CLKID_DEWARPA_DIV                         143
#define CLKID_DEWARPA                             144
#define CLKID_CMPR_MUX                            145
#define CLKID_CMPR_DIV                            146
#define CLKID_CMPR                                147
#define CLKID_HDMITX_SYS_MUX                      148
#define CLKID_HDMITX_SYS_DIV                      149
#define CLKID_HDMITX_SYS                          150
#define CLKID_HDMITX_PRIF_MUX                     151
#define CLKID_HDMITX_PRIF_DIV                     152
#define CLKID_HDMITX_PRIF                         153
#define CLKID_HDMITX_200M_MUX                     154
#define CLKID_HDMITX_200M_DIV                     155
#define CLKID_HDMITX_200M                         156
#define CLKID_HDMITX_AUD_MUX                      157
#define CLKID_HDMITX_AUD_DIV                      158
#define CLKID_HDMITX_AUD                          159
#define CLKID_PWM_A_MUX                           160
#define CLKID_PWM_A_DIV                           161
#define CLKID_PWM_A                               162
#define CLKID_PWM_B_MUX                           163
#define CLKID_PWM_B_DIV                           164
#define CLKID_PWM_B                               165
#define CLKID_PWM_G_MUX                           166
#define CLKID_PWM_G_DIV                           167
#define CLKID_PWM_G                               168
#define CLKID_PWM_H_MUX                           169
#define CLKID_PWM_H_DIV                           170
#define CLKID_PWM_H                               171
#define CLKID_PWM_I_MUX                           172
#define CLKID_PWM_I_DIV                           173
#define CLKID_PWM_I                               174
#define CLKID_PWM_J_MUX                           175
#define CLKID_PWM_J_DIV                           176
#define CLKID_PWM_J                               177
#define CLKID_SPICC0_MUX                          178
#define CLKID_SPICC0_DIV                          179
#define CLKID_SPICC0                              180
#define CLKID_SD_EMMC_A_MUX                       181
#define CLKID_SD_EMMC_A_DIV                       182
#define CLKID_SD_EMMC_A                           183
#define CLKID_SD_EMMC_B_MUX                       184
#define CLKID_SD_EMMC_B_DIV                       185
#define CLKID_SD_EMMC_B                           186
#define CLKID_SD_EMMC_C_MUX                       187
#define CLKID_SD_EMMC_C_DIV                       188
#define CLKID_SD_EMMC_C                           189
#define CLKID_VDIN_MEAS_MUX                       190
#define CLKID_VDIN_MEAS_DIV                       191
#define CLKID_VDIN_MEAS                           192
#define CLKID_VID_LOCK_MUX                        193
#define CLKID_VID_LOCK_DIV                        194
#define CLKID_VID_LOCK                            195
#define CLKID_ETH_CLK_RMII_MUX                    196
#define CLKID_ETH_CLK_RMII_DIV                    197
#define CLKID_ETH_CLK_RMII                        198
#define CLKID_ETH_CLK125M_DIV                     199
#define CLKID_ETH_CLK125M                         200
#define CLKID_TS_DIV                              201
#define CLKID_TS                                  202
#define CLKID_AMFC_MUX                            203
#define CLKID_AMFC_DIV                            204
#define CLKID_AMFC                                205
#define CLKID_CSI2_ADAPT_MUX                      206
#define CLKID_CSI2_ADAPT_DIV                      207
#define CLKID_CSI2_ADAPT                          208
#define CLKID_MIPI_CSI_PHY_0_MUX                  209
#define CLKID_MIPI_CSI_PHY_0_DIV                  210
#define CLKID_MIPI_CSI_PHY_0                      211
#define CLKID_MIPI_CSI_PHY_1_MUX                  212
#define CLKID_MIPI_CSI_PHY_1_DIV                  213
#define CLKID_MIPI_CSI_PHY_1                      214
#define CLKID_MIPI_CSI_PHY                        215
#define CLKID_MIPI_DSI_MEAS_MUX                   216
#define CLKID_MIPI_DSI_MEAS_DIV                   217
#define CLKID_MIPI_DSI_MEAS                       218
#define CLKID_NNA_MUX                             219
#define CLKID_NNA_DIV                             220
#define CLKID_NNA                                 221
#define CLKID_VC9000E_AXI_MUX                     222
#define CLKID_VC9000E_AXI_DIV                     223
#define CLKID_VC9000E_AXI                         224
#define CLKID_VC9000E_CORE_MUX                    225
#define CLKID_VC9000E_CORE_DIV                    226
#define CLKID_VC9000E_CORE                        227
#define CLKID_DSPA_0_MUX                          228
#define CLKID_DSPA_0_DIV                          229
#define CLKID_DSPA_0                              230
#define CLKID_DSPA_1_MUX                          231
#define CLKID_DSPA_1_DIV                          232
#define CLKID_DSPA_1                              233
#define CLKID_DSPA                                234
#define CLKID_PCIE_TL_MUX                         235
#define CLKID_PCIE_TL_DIV                         236
#define CLKID_PCIE_TL                             237
#define CLKID_USB_250M_MUX                        238
#define CLKID_USB_250M_DIV                        239
#define CLKID_USB_250M                            240
#define CLKID_GEN_MUX                             241
#define CLKID_GEN_DIV                             242
#define CLKID_GEN                                 243
#define CLKID_SYS_AM_AXI                          244
#define CLKID_SYS_DOS                             245
#define CLKID_SYS_VC9000E                         246
#define CLKID_SYS_MIPI_DSI                        247
#define CLKID_SYS_ETH_PHY                         248
#define CLKID_SYS_AMFC                            249
#define CLKID_SYS_MALI                            250
#define CLKID_SYS_NNA                             251
#define CLKID_SYS_ETH_MAC                         252
#define CLKID_SYS_AOCPU                           253
#define CLKID_SYS_AUCPU                           254
#define CLKID_SYS_CEC                             255
#define CLKID_SYS_MIPI_DSI_PHY                    256
#define CLKID_SYS_SD_EMMC_A                       257
#define CLKID_SYS_SD_EMMC_B                       258
#define CLKID_SYS_SD_EMMC_C                       259
#define CLKID_SYS_SMARTCARD                       260
#define CLKID_SYS_ACODEC                          261
#define CLKID_SYS_MSR_CLK                         262
#define CLKID_SYS_IR_CTRL                         263
#define CLKID_SYS_AUDIO                           264
#define CLKID_SYS_ETH                             265
#define CLKID_SYS_UART_A                          266
#define CLKID_SYS_UART_B                          267
#define CLKID_SYS_UART_C                          268
#define CLKID_SYS_UART_D                          269
#define CLKID_SYS_UART_E                          270
#define CLKID_SYS_TS_CORE                         271
#define CLKID_SYS_TS_PLL                          272
#define CLKID_SYS_CSI_DIG_CLKIN                   273
#define CLKID_SYS_GE2D                            274
#define CLKID_SYS_SPICC0                          275
#define CLKID_SYS_USB3DRD                         276
#define CLKID_SYS_USB2DRD                         277
#define CLKID_SYS_PCIE_PHY                        278
#define CLKID_SYS_PCIE_MAC                        279
#define CLKID_SYS_I2C_M_A                         280
#define CLKID_SYS_I2C_M_B                         281
#define CLKID_SYS_I2C_M_C                         282
#define CLKID_SYS_I2C_M_D                         283
#define CLKID_SYS_I2C_M_E                         284
#define CLKID_SYS_I2C_M_F                         285
#define CLKID_SYS_HDMITX_APB                      286
#define CLKID_SYS_I2C_S_A                         287
#define CLKID_SYS_HDMI20_AES                      288
#define CLKID_SYS_MMC_APB                         289
#define CLKID_SYS_CSI2_HOST                       290
#define CLKID_SYS_CSI2_ADAPT                      291
#define CLKID_SYS_CPU_APB                         292
#define CLKID_SYS_DSPA                            293
#define CLKID_SYS_VPU_INTR                        294
#define CLKID_SYS_CSI2_PHY0                       295
#define CLKID_SYS_SAR_ADC                         296
#define CLKID_SYS_PWM_J                           297
#define CLKID_SYS_GIC                             298
#define CLKID_SYS_PWM_I                           299
#define CLKID_SYS_PWM_H                           300
#define CLKID_SYS_PWM_G                           301
#define CLKID_SYS_PWM_F                           302
#define CLKID_SYS_PWM_E                           303
#define CLKID_SYS_PWM_D                           304
#define CLKID_SYS_PWM_C                           305
#define CLKID_SYS_PWM_B                           306
#define CLKID_SYS_PWM_A                           307
#define CLKID_AXI_AO_NIC                          308
#define CLKID_AXI_SRAM                            309
#define CLKID_AXI_DEV0_MMC                        310
#define CLKID_AXI_CPU_SRAM                        311

#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S6_CLKC_H */