/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H

#define CLKID_GP0_PLL                             0
#define CLKID_HIFI_PLL                            1
#define CLKID_HDMI_PLL_DCO                        2
#define CLKID_MPLL_PREDIV                         3
#define CLKID_MPLL0                               4
#define CLKID_MPLL0_DIV                           5
#define CLKID_MPLL1                               6
#define CLKID_MPLL1_DIV                           7
#define CLKID_MPLL2                               8
#define CLKID_MPLL2_DIV                           9
#define CLKID_MPLL3                               10
#define CLKID_MPLL3_DIV                           11
#define CLKID_HDMI_PLL_OD                         12
#define CLKID_HDMI_PLL                            13
#define CLKID_FCLK_DIV2_DIV                       14
#define CLKID_FCLK_DIV2                           15
#define CLKID_FCLK_DIV2P5_DIV                     16
#define CLKID_FCLK_DIV2P5                         17
#define CLKID_FCLK_DIV3_DIV                       18
#define CLKID_FCLK_DIV3                           19
#define CLKID_FCLK_DIV4_DIV                       20
#define CLKID_FCLK_DIV4                           21
#define CLKID_FCLK_DIV5_DIV                       22
#define CLKID_FCLK_DIV5                           23
#define CLKID_FCLK_DIV7_DIV                       24
#define CLKID_FCLK_DIV7                           25
#define CLKID_RTC_DUAL_CLKIN                      26
#define CLKID_RTC_DUAL_DIV                        27
#define CLKID_RTC_DUAL_MUX                        28
#define CLKID_RTC_DUAL                            29
#define CLKID_RTC_CLK                             30
#define CLKID_CECA_DUAL_CLKIN                     31
#define CLKID_CECA_DUAL_DIV                       32
#define CLKID_CECA_DUAL_MUX                       33
#define CLKID_CECA_DUAL                           34
#define CLKID_CECA_CLK                            35
#define CLKID_CECB_DUAL_CLKIN                     36
#define CLKID_CECB_DUAL_DIV                       37
#define CLKID_CECB_DUAL_MUX                       38
#define CLKID_CECB_DUAL                           39
#define CLKID_CECB_CLK                            40
#define CLKID_RAMA_0_MUX                          41
#define CLKID_RAMA_0_DIV                          42
#define CLKID_RAMA_0                              43
#define CLKID_RAMA_1_MUX                          44
#define CLKID_RAMA_1_DIV                          45
#define CLKID_RAMA_1                              46
#define CLKID_RAMA                                47
#define CLKID_SAR_ADC_MUX                         48
#define CLKID_SAR_ADC_DIV                         49
#define CLKID_SAR_ADC                             50
#define CLKID_SC_MUX                              51
#define CLKID_SC_DIV                              52
#define CLKID_SC                                  53
#define CLKID_CDAC_MUX                            54
#define CLKID_CDAC_DIV                            55
#define CLKID_CDAC                                56
#define CLKID_VID_PLL_DIV                         57
#define CLKID_VID_PLL_SEL                         58
#define CLKID_VID_PLL                             59
#define CLKID_VIDEO_SRC0_IN_MUX                   60
#define CLKID_VIDEO_SRC0_IN                       61
#define CLKID_VIDEO_SRC0_DIV                      62
#define CLKID_VIDEO_SRC0                          63
#define CLKID_VIDEO_SRC1_IN_MUX                   64
#define CLKID_VIDEO_SRC1_IN                       65
#define CLKID_VIDEO_SRC1_DIV                      66
#define CLKID_VIDEO_SRC1                          67
#define CLKID_VIDEO0_DIV1                         68
#define CLKID_VIDEO0_DIV2_GATE                    69
#define CLKID_VIDEO0_DIV2                         70
#define CLKID_VIDEO0_DIV4_GATE                    71
#define CLKID_VIDEO0_DIV4                         72
#define CLKID_VIDEO0_DIV6_GATE                    73
#define CLKID_VIDEO0_DIV6                         74
#define CLKID_VIDEO0_DIV12_GATE                   75
#define CLKID_VIDEO0_DIV12                        76
#define CLKID_VIDEO2_DIV1                         77
#define CLKID_VIDEO2_DIV2_GATE                    78
#define CLKID_VIDEO2_DIV2                         79
#define CLKID_VIDEO2_DIV4_GATE                    80
#define CLKID_VIDEO2_DIV4                         81
#define CLKID_VIDEO2_DIV6_GATE                    82
#define CLKID_VIDEO2_DIV6                         83
#define CLKID_VIDEO2_DIV12_GATE                   84
#define CLKID_VIDEO2_DIV12                        85
#define CLKID_LCD_AN_MUX                          86
#define CLKID_LCD_AN                              87
#define CLKID_LCD_AN_PH2                          88
#define CLKID_LCD_AN_PH3                          89
#define CLKID_HDMITX_PIXEL_MUX                    90
#define CLKID_HDMITX_PIXEL                        91
#define CLKID_ENCI_MUX                            92
#define CLKID_ENCI                                93
#define CLKID_ENCP_MUX                            94
#define CLKID_ENCP                                95
#define CLKID_ENCT_MUX                            96
#define CLKID_ENCT                                97
#define CLKID_ENCL_MUX                            98
#define CLKID_ENCL                                99
#define CLKID_VDAC_MUX                            100
#define CLKID_VDAC                                101
#define CLKID_VID_LOCK_MUX                        102
#define CLKID_VID_LOCK_DIV                        103
#define CLKID_VID_LOCK                            104
#define CLKID_MALI_0_MUX                          105
#define CLKID_MALI_0_DIV                          106
#define CLKID_MALI_0                              107
#define CLKID_MALI_1_MUX                          108
#define CLKID_MALI_1_DIV                          109
#define CLKID_MALI_1                              110
#define CLKID_MALI                                111
#define CLKID_VDEC_0_MUX                          112
#define CLKID_VDEC_0_DIV                          113
#define CLKID_VDEC_0                              114
#define CLKID_VDEC_1_MUX                          115
#define CLKID_VDEC_1_DIV                          116
#define CLKID_VDEC_1                              117
#define CLKID_VDEC                                118
#define CLKID_HEVCF_0_MUX                         119
#define CLKID_HEVCF_0_DIV                         120
#define CLKID_HEVCF_0                             121
#define CLKID_HEVCF_1_MUX                         122
#define CLKID_HEVCF_1_DIV                         123
#define CLKID_HEVCF_1                             124
#define CLKID_HEVCF                               125
#define CLKID_VPU_0_MUX                           126
#define CLKID_VPU_0_DIV                           127
#define CLKID_VPU_0                               128
#define CLKID_VPU_1_MUX                           129
#define CLKID_VPU_1_DIV                           130
#define CLKID_VPU_1                               131
#define CLKID_VPU                                 132
#define CLKID_VPU_CLKB_TMP_MUX                    133
#define CLKID_VPU_CLKB_TMP_DIV                    134
#define CLKID_VPU_CLKB_TMP                        135
#define CLKID_VPU_CLKB_DIV                        136
#define CLKID_VPU_CLKB                            137
#define CLKID_VPU_CLKC_0_MUX                      138
#define CLKID_VPU_CLKC_0_DIV                      139
#define CLKID_VPU_CLKC_0                          140
#define CLKID_VPU_CLKC_1_MUX                      141
#define CLKID_VPU_CLKC_1_DIV                      142
#define CLKID_VPU_CLKC_1                          143
#define CLKID_VPU_CLKC                            144
#define CLKID_VAPB_0_MUX                          145
#define CLKID_VAPB_0_DIV                          146
#define CLKID_VAPB_0                              147
#define CLKID_VAPB_1_MUX                          148
#define CLKID_VAPB_1_DIV                          149
#define CLKID_VAPB_1                              150
#define CLKID_VAPB                                151
#define CLKID_GE2D                                152
#define CLKID_VDIN_MEAS_MUX                       153
#define CLKID_VDIN_MEAS_DIV                       154
#define CLKID_VDIN_MEAS                           155
#define CLKID_SD_EMMC_A_MUX                       156
#define CLKID_SD_EMMC_A_DIV                       157
#define CLKID_SD_EMMC_A                           158
#define CLKID_SD_EMMC_B_MUX                       159
#define CLKID_SD_EMMC_B_DIV                       160
#define CLKID_SD_EMMC_B                           161
#define CLKID_SD_EMMC_C_MUX                       162
#define CLKID_SD_EMMC_C_DIV                       163
#define CLKID_SD_EMMC_C                           164
#define CLKID_SPICC0_MUX                          165
#define CLKID_SPICC0_DIV                          166
#define CLKID_SPICC0                              167
#define CLKID_PWM_A_MUX                           168
#define CLKID_PWM_A_DIV                           169
#define CLKID_PWM_A                               170
#define CLKID_PWM_B_MUX                           171
#define CLKID_PWM_B_DIV                           172
#define CLKID_PWM_B                               173
#define CLKID_PWM_C_MUX                           174
#define CLKID_PWM_C_DIV                           175
#define CLKID_PWM_C                               176
#define CLKID_PWM_D_MUX                           177
#define CLKID_PWM_D_DIV                           178
#define CLKID_PWM_D                               179
#define CLKID_PWM_E_MUX                           180
#define CLKID_PWM_E_DIV                           181
#define CLKID_PWM_E                               182
#define CLKID_PWM_F_MUX                           183
#define CLKID_PWM_F_DIV                           184
#define CLKID_PWM_F                               185
#define CLKID_PWM_G_MUX                           186
#define CLKID_PWM_G_DIV                           187
#define CLKID_PWM_G                               188
#define CLKID_PWM_H_MUX                           189
#define CLKID_PWM_H_DIV                           190
#define CLKID_PWM_H                               191
#define CLKID_PWM_I_MUX                           192
#define CLKID_PWM_I_DIV                           193
#define CLKID_PWM_I                               194
#define CLKID_PWM_J_MUX                           195
#define CLKID_PWM_J_DIV                           196
#define CLKID_PWM_J                               197
#define CLKID_HDMITX_SYS_MUX                      198
#define CLKID_HDMITX_SYS_DIV                      199
#define CLKID_HDMITX_SYS                          200
#define CLKID_HDCP22_ESM_MUX                      201
#define CLKID_HDCP22_ESM_DIV                      202
#define CLKID_HDCP22_ESM                          203
#define CLKID_HDCP22_SKP_MUX                      204
#define CLKID_HDCP22_SKP_DIV                      205
#define CLKID_HDCP22_SKP                          206
#define CLKID_DEMOD_CORE_MUX                      207
#define CLKID_DEMOD_CORE_DIV                      208
#define CLKID_DEMOD_CORE                          209
#define CLKID_DEMOD_CORE_T2_MUX                   210
#define CLKID_DEMOD_CORE_T2_DIV                   211
#define CLKID_DEMOD_CORE_T2                       212
#define CLKID_DEMOD_32K_CLKIN                     213
#define CLKID_DEMOD_32K_DIV                       214
#define CLKID_DEMOD_32K_MUX                       215
#define CLKID_DEMOD_32K                           216
#define CLKID_ADC_EXTCLK_IN_MUX                   217
#define CLKID_ADC_EXTCLK_IN_DIV                   218
#define CLKID_ADC_EXTCLK_IN                       219
#define CLKID_ETH_CLK_RMII_DIV                    220
#define CLKID_ETH_CLK_RMII                        221
#define CLKID_ETH_CLK125M_DIV                     222
#define CLKID_ETH_CLK125M                         223
#define CLKID_TS_DIV                              224
#define CLKID_TS                                  225
#define CLKID_GEN_MUX                             226
#define CLKID_GEN_DIV                             227
#define CLKID_GEN                                 228
#define CLKID_SYS_DDR                             229
#define CLKID_SYS_DOS                             230
#define CLKID_SYS_ETH_PHY                         231
#define CLKID_SYS_MALI                            232
#define CLKID_SYS_AOCPU                           233
#define CLKID_SYS_AUCPU                           234
#define CLKID_SYS_CEC                             235
#define CLKID_SYS_SD_EMMC_A                       236
#define CLKID_SYS_SD_EMMC_B                       237
#define CLKID_SYS_SD_EMMC_C                       238
#define CLKID_SYS_SMARTCARD                       239
#define CLKID_SYS_ACODEC                          240
#define CLKID_SYS_SPIFC                           241
#define CLKID_SYS_MSR_CLK                         242
#define CLKID_SYS_IR_CTRL                         243
#define CLKID_SYS_AUDIO                           244
#define CLKID_SYS_ETH                             245
#define CLKID_SYS_UART_A                          246
#define CLKID_SYS_UART_B                          247
#define CLKID_SYS_UART_C                          248
#define CLKID_SYS_UART_D                          249
#define CLKID_SYS_UART_E                          250
#define CLKID_SYS_AIFIFO                          251
#define CLKID_SYS_TS_DDR                          252
#define CLKID_SYS_TS_PLL                          253
#define CLKID_SYS_GE2D                            254
#define CLKID_SYS_SPICC0                          255
#define CLKID_SYS_USB                             256
#define CLKID_SYS_I2C_M_A                         257
#define CLKID_SYS_I2C_M_B                         258
#define CLKID_SYS_I2C_M_C                         259
#define CLKID_SYS_I2C_M_D                         260
#define CLKID_SYS_I2C_M_E                         261
#define CLKID_SYS_I2C_M_F                         262
#define CLKID_SYS_HDMITX_APB                      263
#define CLKID_SYS_I2C_S_A                         264
#define CLKID_SYS_USB1_TO_DDR                     265
#define CLKID_SYS_HDCP22                          266
#define CLKID_SYS_MMC_APB                         267
#define CLKID_SYS_RSA                             268
#define CLKID_SYS_CPU_DEBUG                       269
#define CLKID_SYS_VPU_INTR                        270
#define CLKID_SYS_DEMOD                           271
#define CLKID_SYS_SAR_ADC                         272
#define CLKID_SYS_GIC                             273
#define CLKID_SYS_PWM_AB                          274
#define CLKID_SYS_PWM_CD                          275
#define CLKID_SYS_PWM_EF                          276
#define CLKID_SYS_PWM_GH                          277
#define CLKID_SYS_PWM_IJ                          278

#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H */