/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2019 Amlogic, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C4_CLKC_H #define _DT_BINDINGS_CLOCK_AMLOGIC_C4_CLKC_H #define CLKID_GP0_PLL 0 #define CLKID_HIFI_PLL 1 #define CLKID_MCLK_PLL 2 #define CLKID_FCLK_50M_DIV 3 #define CLKID_FCLK_50M 4 #define CLKID_FCLK_DIV2_DIV 5 #define CLKID_FCLK_DIV2 6 #define CLKID_FCLK_DIV2P5_DIV 7 #define CLKID_FCLK_DIV2P5 8 #define CLKID_FCLK_DIV3_DIV 9 #define CLKID_FCLK_DIV3 10 #define CLKID_FCLK_DIV4_DIV 11 #define CLKID_FCLK_DIV4 12 #define CLKID_FCLK_DIV5_DIV 13 #define CLKID_FCLK_DIV5 14 #define CLKID_FCLK_DIV7_DIV 15 #define CLKID_FCLK_DIV7 16 #define CLKID_MCLK_PLL_CLK 17 #define CLKID_MCLK0_MUX 18 #define CLKID_MCLK0_DIV 19 #define CLKID_MCLK0 20 #define CLKID_MCLK1_MUX 21 #define CLKID_MCLK1_DIV 22 #define CLKID_MCLK1 23 #define CLKID_RTC_DUAL_CLKIN 24 #define CLKID_RTC_DUAL_DIV 25 #define CLKID_RTC_DUAL_MUX 26 #define CLKID_RTC_DUAL 27 #define CLKID_RTC_CLK 28 #define CLKID_SAR_ADC_MUX 29 #define CLKID_SAR_ADC_DIV 30 #define CLKID_SAR_ADC 31 #define CLKID_NNA_MUX 32 #define CLKID_NNA_DIV 33 #define CLKID_NNA 34 #define CLKID_PWM_C_MUX 35 #define CLKID_PWM_C_DIV 36 #define CLKID_PWM_C 37 #define CLKID_PWM_D_MUX 38 #define CLKID_PWM_D_DIV 39 #define CLKID_PWM_D 40 #define CLKID_PWM_E_MUX 41 #define CLKID_PWM_E_DIV 42 #define CLKID_PWM_E 43 #define CLKID_PWM_F_MUX 44 #define CLKID_PWM_F_DIV 45 #define CLKID_PWM_F 46 #define CLKID_PWM_G_MUX 47 #define CLKID_PWM_G_DIV 48 #define CLKID_PWM_G 49 #define CLKID_PWM_H_MUX 50 #define CLKID_PWM_H_DIV 51 #define CLKID_PWM_H 52 #define CLKID_PWM_I_MUX 53 #define CLKID_PWM_I_DIV 54 #define CLKID_PWM_I 55 #define CLKID_PWM_J_MUX 56 #define CLKID_PWM_J_DIV 57 #define CLKID_PWM_J 58 #define CLKID_PWM_K_MUX 59 #define CLKID_PWM_K_DIV 60 #define CLKID_PWM_K 61 #define CLKID_PWM_L_MUX 62 #define CLKID_PWM_L_DIV 63 #define CLKID_PWM_L 64 #define CLKID_PWM_M_MUX 65 #define CLKID_PWM_M_DIV 66 #define CLKID_PWM_M 67 #define CLKID_PWM_N_MUX 68 #define CLKID_PWM_N_DIV 69 #define CLKID_PWM_N 70 #define CLKID_SPICC0_MUX 71 #define CLKID_SPICC0_DIV 72 #define CLKID_SPICC0 73 #define CLKID_SPICC1_MUX 74 #define CLKID_SPICC1_DIV 75 #define CLKID_SPICC1 76 #define CLKID_SD_EMMC_A_MUX 77 #define CLKID_SD_EMMC_A_DIV 78 #define CLKID_SD_EMMC_A 79 #define CLKID_SD_EMMC_B_MUX 80 #define CLKID_SD_EMMC_B_DIV 81 #define CLKID_SD_EMMC_B 82 #define CLKID_SD_EMMC_C_MUX 83 #define CLKID_SD_EMMC_C_DIV 84 #define CLKID_SD_EMMC_C 85 #define CLKID_ETH_RMII_MUX 86 #define CLKID_ETH_RMII_DIV 87 #define CLKID_ETH_RMII 88 #define CLKID_ETH_125M_DIV 89 #define CLKID_ETH_125M 90 #define CLKID_TS_DIV 91 #define CLKID_TS 92 #define CLKID_HCODEC_0_MUX 93 #define CLKID_HCODEC_0_DIV 94 #define CLKID_HCODEC_0 95 #define CLKID_HCODEC_1_MUX 96 #define CLKID_HCODEC_1_DIV 97 #define CLKID_HCODEC_1 98 #define CLKID_HCODEC 99 #define CLKID_TAHOE_MUX 100 #define CLKID_TAHOE_DIV 101 #define CLKID_TAHOE 102 #define CLKID_CVE_MUX 103 #define CLKID_CVE_DIV 104 #define CLKID_CVE 105 #define CLKID_CVE_ARB_MUX 106 #define CLKID_CVE_ARB_DIV 107 #define CLKID_CVE_ARB 108 #define CLKID_GE2D_MUX 109 #define CLKID_GE2D_DIV 110 #define CLKID_GE2D 111 #define CLKID_DEWARP_MUX 112 #define CLKID_DEWARP_DIV 113 #define CLKID_DEWARP 114 #define CLKID_ISP_MUX 115 #define CLKID_ISP_DIV 116 #define CLKID_ISP 117 #define CLKID_CSI_PHY_MUX 118 #define CLKID_CSI_PHY_DIV 119 #define CLKID_CSI_PHY 120 #define CLKID_AMFC_MUX 121 #define CLKID_AMFC_DIV 122 #define CLKID_AMFC 123 #define CLKID_CLK_24M_IN 124 #define CLKID_CLK_12M_DIV 125 #define CLKID_CLK_12M 126 #define CLKID_GEN_MUX 127 #define CLKID_GEN_DIV 128 #define CLKID_GEN 129 #define CLKID_SYS_CLK_CTRL 130 #define CLKID_SYS_RESET_CTRL 131 #define CLKID_SYS_ANALOG_CTRL 132 #define CLKID_SYS_PWR_CTRL 133 #define CLKID_SYS_PAD_CTRL 134 #define CLKID_SYS_SYS_CTRL 135 #define CLKID_SYS_TS_PLL 136 #define CLKID_SYS_MMC_PCLK 137 #define CLKID_SYS_CAPU 138 #define CLKID_SYS_CPU_CTRL 139 #define CLKID_SYS_JTAG_CTRL 140 #define CLKID_SYS_IRQ_CTRL 141 #define CLKID_SYS_MSR_CLK 142 #define CLKID_SYS_ROM 143 #define CLKID_SYS_UART_F 144 #define CLKID_SYS_CPU_APB 145 #define CLKID_SYS_SAR_ADC 146 #define CLKID_SYS_STARTUP 147 #define CLKID_SYS_SECURE 148 #define CLKID_SYS_AMFC 149 #define CLKID_SYS_NNA 150 #define CLKID_SYS_ETH_MAC 151 #define CLKID_SYS_GIC 152 #define CLKID_SYS_RAMA 153 #define CLKID_SYS_BIG_NIC 154 #define CLKID_SYS_AUDIO_VAD 155 #define CLKID_SYS_AUDIO 156 #define CLKID_SYS_PWM_A 157 #define CLKID_SYS_PWM_B 158 #define CLKID_SYS_USB 159 #define CLKID_SYS_SD_EMMC_A 160 #define CLKID_SYS_SD_EMMC_C 161 #define CLKID_SYS_PWM_C 162 #define CLKID_SYS_PWM_D 163 #define CLKID_SYS_PWM_E 164 #define CLKID_SYS_PWM_F 165 #define CLKID_SYS_PIO_CORE 166 #define CLKID_SYS_SPICC 167 #define CLKID_SYS_UART_A 168 #define CLKID_SYS_UART_B 169 #define CLKID_SYS_UART_C 170 #define CLKID_SYS_UART_D 171 #define CLKID_SYS_UART_E 172 #define CLKID_SYS_I2C_M_A 173 #define CLKID_SYS_I2C_M_B 174 #define CLKID_SYS_I2C_M_C 175 #define CLKID_SYS_I2C_M_D 176 #define CLKID_SYS_I2C_S_A 177 #define CLKID_SYS_ETH_PHY 178 #define CLKID_SYS_ACODEC 179 #define CLKID_SYS_PWM_N 180 #define CLKID_SYS_DOS 181 #define CLKID_SYS_CVE 182 #define CLKID_SYS_ISP_CAPU 183 #define CLKID_SYS_TAHOE 184 #define CLKID_SYS_CVE_INTR 185 #define CLKID_SYS_SD_EMMC_B 186 #define CLKID_SYS_PWM_G 187 #define CLKID_SYS_PWM_H 188 #define CLKID_SYS_PWM_I 189 #define CLKID_SYS_PWM_J 190 #define CLKID_SYS_PWM_K 191 #define CLKID_SYS_PWM_L 192 #define CLKID_SYS_PWM_M 193 #define CLKID_AXI_SYS_NIC 194 #define CLKID_AXI_RAMA 195 #define CLKID_AXI_MUX_NIC 196 #define CLKID_AXI_DEV_DMC 197 /** * ao clk ids */ #define CLKID_AO_ROUGH_32K_CLK_DIV 0 #define CLKID_AO_ROUGH_32K_CLK 1 #define CLKID_AO_OSCIN32K_CLK 2 #define CLKID_AO_OSCIN_CLK 3 #define CLKID_AO_SYS_CLK 4 #define CLKID_AO_PWM_J_MUX 5 #define CLKID_AO_PWM_J_DIV 6 #define CLKID_AO_PWM_J 7 #define CLKID_AO_PWM_K_MUX 8 #define CLKID_AO_PWM_K_DIV 9 #define CLKID_AO_PWM_K 10 #define CLKID_AO_SYS_APB_CLK 11 #define CLKID_AO_SYS_RTC_REG 12 #define CLKID_AO_SYS_RTC_CLK 13 #define CLKID_AO_SYS_RESET_CTRL 14 #define CLKID_AO_SYS_PAD_CTRL 15 #define CLKID_AO_SYS_RTC_DIG 16 #define CLKID_AO_SYS_IRQ_CTRL 17 #define CLKID_AO_SYS_PWR_CTRL 18 #define CLKID_AO_SYS_PWM_J 19 #define CLKID_AO_SYS_PWM_K 20 #define CLKID_AO_SYS_SED 21 #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C4_CLKC_H */