/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2025 Amlogic, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A9_CLKC_H #define _DT_BINDINGS_CLOCK_AMLOGIC_A9_CLKC_H #define CLKID_GP0_PLL 0 #define CLKID_HIFI_PLL 1 #define CLKID_HIFI1_PLL 2 #define CLKID_MCLK_PLL 3 #define CLKID_MCLK1_PLL 4 #define CLKID_MCLK_0_PRE_DIV 5 #define CLKID_MCLK_0_PRE 6 #define CLKID_MCLK_0_MUX 7 #define CLKID_MCLK_0_DIV 8 #define CLKID_MCLK_0 9 #define CLKID_MCLK_1_PRE_DIV 10 #define CLKID_MCLK_1_PRE 11 #define CLKID_MCLK_1_MUX 12 #define CLKID_MCLK_1_DIV 13 #define CLKID_MCLK_1 14 #define CLKID_MCLK1_0_PRE_DIV 15 #define CLKID_MCLK1_0_PRE 16 #define CLKID_MCLK1_0_MUX 17 #define CLKID_MCLK1_0_DIV 18 #define CLKID_MCLK1_0 19 #define CLKID_MCLK1_1_PRE_DIV 20 #define CLKID_MCLK1_1_PRE 21 #define CLKID_MCLK1_1_MUX 22 #define CLKID_MCLK1_1_DIV 23 #define CLKID_MCLK1_1 24 #define CLKID_SAR_ADC_MUX 25 #define CLKID_SAR_ADC_DIV 26 #define CLKID_SAR_ADC 27 #define CLKID_SC_PRE_MUX 28 #define CLKID_SC_PRE_DIV 29 #define CLKID_SC_PRE 30 #define CLKID_SC 31 #define CLKID_VIDEO_SRC0_IN_MUX 32 #define CLKID_VIDEO_SRC0_IN 33 #define CLKID_VIDEO_SRC0_DIV 34 #define CLKID_VIDEO_SRC0 35 #define CLKID_VIDEO_SRC1_IN_MUX 36 #define CLKID_VIDEO_SRC1_IN 37 #define CLKID_VIDEO_SRC1_DIV 38 #define CLKID_VIDEO_SRC1 39 #define CLKID_VIDEO0_DIV1 40 #define CLKID_VIDEO0_DIV2_EN 41 #define CLKID_VIDEO0_DIV2 42 #define CLKID_VIDEO0_DIV4_EN 43 #define CLKID_VIDEO0_DIV4 44 #define CLKID_VIDEO0_DIV6_EN 45 #define CLKID_VIDEO0_DIV6 46 #define CLKID_VIDEO0_DIV12_EN 47 #define CLKID_VIDEO0_DIV12 48 #define CLKID_VIDEO1_DIV1 49 #define CLKID_VIDEO1_DIV2_EN 50 #define CLKID_VIDEO1_DIV2 51 #define CLKID_VIDEO1_DIV4_EN 52 #define CLKID_VIDEO1_DIV4 53 #define CLKID_VIDEO1_DIV6_EN 54 #define CLKID_VIDEO1_DIV6 55 #define CLKID_VIDEO1_DIV12_EN 56 #define CLKID_VIDEO1_DIV12 57 #define CLKID_LCD_AN_MUX 58 #define CLKID_LCD_AN 59 #define CLKID_LCD_AN_PH2 60 #define CLKID_LCD_AN_PH3 61 #define CLKID_ENC0_MUX 62 #define CLKID_ENC0 63 #define CLKID_ENC1_MUX 64 #define CLKID_ENC1 65 #define CLKID_VDAC_MUX 66 #define CLKID_VDAC 67 #define CLKID_HDMITX_PIXEL_MUX 68 #define CLKID_HDMITX_PIXEL 69 #define CLKID_HDMITX_FE_MUX 70 #define CLKID_HDMITX_FE 71 #define CLKID_HDMITX1_PIXEL_MUX 72 #define CLKID_HDMITX1_PIXEL 73 #define CLKID_HDMITX1_FE_MUX 74 #define CLKID_HDMITX1_FE 75 #define CLKID_MALI_0_MUX 76 #define CLKID_MALI_0_DIV 77 #define CLKID_MALI_0 78 #define CLKID_MALI_1_MUX 79 #define CLKID_MALI_1_DIV 80 #define CLKID_MALI_1 81 #define CLKID_MALI 82 #define CLKID_MALI_STACK_0_MUX 83 #define CLKID_MALI_STACK_0_DIV 84 #define CLKID_MALI_STACK_0 85 #define CLKID_MALI_STACK_1_MUX 86 #define CLKID_MALI_STACK_1_DIV 87 #define CLKID_MALI_STACK_1 88 #define CLKID_MALI_STACK 89 #define CLKID_HEVCF_0_MUX 90 #define CLKID_HEVCF_0_DIV 91 #define CLKID_HEVCF_0 92 #define CLKID_HEVCF_1_MUX 93 #define CLKID_HEVCF_1_DIV 94 #define CLKID_HEVCF_1 95 #define CLKID_HEVCF 96 #define CLKID_HCODEC_0_MUX 97 #define CLKID_HCODEC_0_DIV 98 #define CLKID_HCODEC_0 99 #define CLKID_HCODEC_1_MUX 100 #define CLKID_HCODEC_1_DIV 101 #define CLKID_HCODEC_1 102 #define CLKID_HCODEC 103 #define CLKID_VPU_0_MUX 104 #define CLKID_VPU_0_DIV 105 #define CLKID_VPU_0 106 #define CLKID_VPU_1_MUX 107 #define CLKID_VPU_1_DIV 108 #define CLKID_VPU_1 109 #define CLKID_VPU 110 #define CLKID_VPU_CLKB_TMP_MUX 111 #define CLKID_VPU_CLKB_TMP_DIV 112 #define CLKID_VPU_CLKB_TMP 113 #define CLKID_VPU_CLKB_DIV 114 #define CLKID_VPU_CLKB 115 #define CLKID_VAPB_0_MUX 116 #define CLKID_VAPB_0_DIV 117 #define CLKID_VAPB_0 118 #define CLKID_VAPB_1_MUX 119 #define CLKID_VAPB_1_DIV 120 #define CLKID_VAPB_1 121 #define CLKID_VAPB 122 #define CLKID_GE2D 123 #define CLKID_HDMITX_SYS_MUX 124 #define CLKID_HDMITX_SYS_DIV 125 #define CLKID_HDMITX_SYS 126 #define CLKID_HDMITX_PRIF_MUX 127 #define CLKID_HDMITX_PRIF_DIV 128 #define CLKID_HDMITX_PRIF 129 #define CLKID_HDMITX_200M_MUX 130 #define CLKID_HDMITX_200M_DIV 131 #define CLKID_HDMITX_200M 132 #define CLKID_HDMITX_AUD_MUX 133 #define CLKID_HDMITX_AUD_DIV 134 #define CLKID_HDMITX_AUD 135 #define CLKID_PWM_H_MUX 136 #define CLKID_PWM_H_DIV 137 #define CLKID_PWM_H 138 #define CLKID_PWM_I_MUX 139 #define CLKID_PWM_I_DIV 140 #define CLKID_PWM_I 141 #define CLKID_PWM_J_MUX 142 #define CLKID_PWM_J_DIV 143 #define CLKID_PWM_J 144 #define CLKID_PWM_K_MUX 145 #define CLKID_PWM_K_DIV 146 #define CLKID_PWM_K 147 #define CLKID_PWM_L_MUX 148 #define CLKID_PWM_L_DIV 149 #define CLKID_PWM_L 150 #define CLKID_PWM_M_MUX 151 #define CLKID_PWM_M_DIV 152 #define CLKID_PWM_M 153 #define CLKID_PWM_N_MUX 154 #define CLKID_PWM_N_DIV 155 #define CLKID_PWM_N 156 #define CLKID_SPISG0_MUX 157 #define CLKID_SPISG0_DIV 158 #define CLKID_SPISG0 159 #define CLKID_SPISG1_MUX 160 #define CLKID_SPISG1_DIV 161 #define CLKID_SPISG1 162 #define CLKID_SPISG2_MUX 163 #define CLKID_SPISG2_DIV 164 #define CLKID_SPISG2 165 #define CLKID_SD_EMMC_A_MUX 166 #define CLKID_SD_EMMC_A_DIV 167 #define CLKID_SD_EMMC_A 168 #define CLKID_SD_EMMC_B_MUX 169 #define CLKID_SD_EMMC_B_DIV 170 #define CLKID_SD_EMMC_B 171 #define CLKID_SD_EMMC_C_MUX 172 #define CLKID_SD_EMMC_C_DIV 173 #define CLKID_SD_EMMC_C 174 #define CLKID_VDIN_MEAS_MUX 175 #define CLKID_VDIN_MEAS_DIV 176 #define CLKID_VDIN_MEAS 177 #define CLKID_VID_LOCK_MUX 178 #define CLKID_VID_LOCK_DIV 179 #define CLKID_VID_LOCK 180 #define CLKID_ETH_RMII_MUX 181 #define CLKID_ETH_RMII_DIV 182 #define CLKID_ETH_RMII 183 #define CLKID_ETH_125M_DIV 184 #define CLKID_ETH_125M 185 #define CLKID_TS_DIV 186 #define CLKID_TS 187 #define CLKID_AMFC_MUX 188 #define CLKID_AMFC_DIV 189 #define CLKID_AMFC 190 #define CLKID_PCIE0_TL_MUX 191 #define CLKID_PCIE0_TL_DIV 192 #define CLKID_PCIE0_TL 193 #define CLKID_PCIE1_TL_MUX 194 #define CLKID_PCIE1_TL_DIV 195 #define CLKID_PCIE1_TL 196 #define CLKID_PP_MUX 197 #define CLKID_PP_DIV 198 #define CLKID_PP 199 #define CLKID_ISP_MUX 200 #define CLKID_ISP_DIV 201 #define CLKID_ISP 202 #define CLKID_DSPA_0_MUX 203 #define CLKID_DSPA_0_DIV 204 #define CLKID_DSPA_0 205 #define CLKID_DSPA_1_MUX 206 #define CLKID_DSPA_1_DIV 207 #define CLKID_DSPA_1 208 #define CLKID_DSPA 209 #define CLKID_GLB_MUX 210 #define CLKID_GLB_DIV 211 #define CLKID_GLB 212 #define CLKID_CAN0_PE_MUX 213 #define CLKID_CAN0_PE_DIV 214 #define CLKID_CAN0_PE 215 #define CLKID_CAN1_PE_MUX 216 #define CLKID_CAN1_PE_DIV 217 #define CLKID_CAN1_PE 218 #define CLKID_CAN0_FILTER_MUX 219 #define CLKID_CAN0_FILTER_DIV 220 #define CLKID_CAN0_FILTER 221 #define CLKID_CAN1_FILTER_MUX 222 #define CLKID_CAN1_FILTER_DIV 223 #define CLKID_CAN1_FILTER 224 #define CLKID_I3C_MUX 225 #define CLKID_I3C_DIV 226 #define CLKID_I3C 227 #define CLKID_CMPR_MUX 228 #define CLKID_CMPR_DIV 229 #define CLKID_CMPR 230 #define CLKID_VGE_MUX 231 #define CLKID_VGE_DIV 232 #define CLKID_VGE 233 #define CLKID_CVE_MUX 234 #define CLKID_CVE_DIV 235 #define CLKID_CVE 236 #define CLKID_DEWARPA_MUX 237 #define CLKID_DEWARPA_DIV 238 #define CLKID_DEWARPA 239 #define CLKID_DPTX_APB2_MUX 240 #define CLKID_DPTX_APB2_DIV 241 #define CLKID_DPTX_APB2 242 #define CLKID_DPTX_AUD_MUX 243 #define CLKID_DPTX_AUD_DIV 244 #define CLKID_DPTX_AUD 245 #define CLKID_DSI_MEAS_MUX 246 #define CLKID_DSI_MEAS_DIV 247 #define CLKID_DSI_MEAS 248 #define CLKID_DSI_B_MEAS_MUX 249 #define CLKID_DSI_B_MEAS_DIV 250 #define CLKID_DSI_B_MEAS 251 #define CLKID_HDMIRX_2M_MUX 252 #define CLKID_HDMIRX_2M_DIV 253 #define CLKID_HDMIRX_2M 254 #define CLKID_HDMIRX_5M_MUX 255 #define CLKID_HDMIRX_5M_DIV 256 #define CLKID_HDMIRX_5M 257 #define CLKID_HDMIRX_CFG_MUX 258 #define CLKID_HDMIRX_CFG_DIV 259 #define CLKID_HDMIRX_CFG 260 #define CLKID_HDMIRX_HDCP2X_MUX 261 #define CLKID_HDMIRX_HDCP2X_DIV 262 #define CLKID_HDMIRX_HDCP2X 263 #define CLKID_HDMIRX_ACR_REF_MUX 264 #define CLKID_HDMIRX_ACR_REF_DIV 265 #define CLKID_HDMIRX_ACR_REF 266 #define CLKID_HDMIRX_METER_MUX 267 #define CLKID_HDMIRX_METER_DIV 268 #define CLKID_HDMIRX_METER 269 #define CLKID_USB_250M_MUX 270 #define CLKID_USB_250M_DIV 271 #define CLKID_USB_250M 272 #define CLKID_NNA_CORE_MUX 273 #define CLKID_NNA_CORE_DIV 274 #define CLKID_NNA_CORE 275 #define CLKID_CSI_PHY_MUX 276 #define CLKID_CSI_PHY_DIV 277 #define CLKID_CSI_PHY 278 #define CLKID_USB_48M_PRE_MUX 279 #define CLKID_USB_48M_PRE_DIV 280 #define CLKID_USB_48M_PRE 281 #define CLKID_USB_48M_DUAL_CLKIN 282 #define CLKID_USB_48M_DUAL_DIV 283 #define CLKID_USB_48M_DUAL_MUX 284 #define CLKID_USB_48M_DUAL 285 #define CLKID_USB_48M 286 #define CLKID_GEN_MUX 287 #define CLKID_GEN_DIV 288 #define CLKID_GEN 289 #define CLKID_SYS_AM_AXI 290 #define CLKID_SYS_DOS 291 #define CLKID_SYS_MIPI_DSI 292 #define CLKID_SYS_ETH_PHY 293 #define CLKID_SYS_AMFC 294 #define CLKID_SYS_MALI 295 #define CLKID_SYS_NNA 296 #define CLKID_SYS_ETH_AXI 297 #define CLKID_SYS_DP_APB 298 #define CLKID_SYS_EDPTX_APB 299 #define CLKID_SYS_U3HSG 300 #define CLKID_SYS_AUCPU 301 #define CLKID_SYS_GLB 302 #define CLKID_SYS_COMBO_DPHY_APB 303 #define CLKID_SYS_HDMIRX_APB 304 #define CLKID_SYS_HDMIRX_PCLK 305 #define CLKID_SYS_MIPI_DSI_PHY 306 #define CLKID_SYS_CAN1 307 #define CLKID_SYS_CAN0 308 #define CLKID_SYS_SD_EMMC_A 309 #define CLKID_SYS_SD_EMMC_B 310 #define CLKID_SYS_SD_EMMC_C 311 #define CLKID_SYS_SC 312 #define CLKID_SYS_ACODEC 313 #define CLKID_SYS_MIPI_ISP 314 #define CLKID_SYS_MSR_CLK 315 #define CLKID_SYS_AUDIO 316 #define CLKID_SYS_MIPI_DSI_B 317 #define CLKID_SYS_MIPI_DSI1_PHY 318 #define CLKID_SYS_ETH 319 #define CLKID_SYS_ETH_1G_MAC 320 #define CLKID_SYS_UART_A 321 #define CLKID_SYS_UART_F 322 #define CLKID_SYS_TS_A55 323 #define CLKID_SYS_ETH_1G_AXI 324 #define CLKID_SYS_TS_DOS 325 #define CLKID_SYS_USB3DRD_B 326 #define CLKID_SYS_TS_CORE 327 #define CLKID_SYS_TS_PLL 328 #define CLKID_SYS_CSI_DIG_CLKIN 329 #define CLKID_SYS_CVE 330 #define CLKID_SYS_GE2D 331 #define CLKID_SYS_SPISG0 332 #define CLKID_SYS_U3DRD_1 333 #define CLKID_SYS_U2H 334 #define CLKID_SYS_PCIEMAC_A 335 #define CLKID_SYS_USB3DRD_A 336 #define CLKID_SYS_USB2DRD 337 #define CLKID_SYS_PCIEPHY 338 #define CLKID_SYS_PCIEMAC_B 339 #define CLKID_SYS_PERIPH 340 #define CLKID_SYS_PIO 341 #define CLKID_SYS_I3C 342 #define CLKID_SYS_I2C_M_E 343 #define CLKID_SYS_I2C_M_F 344 #define CLKID_SYS_HDMITX_APB 345 #define CLKID_SYS_I2C_M_I 346 #define CLKID_SYS_I2C_M_G 347 #define CLKID_SYS_I2C_M_H 348 #define CLKID_SYS_HDMI20_AES 349 #define CLKID_SYS_CSI2_HOST 350 #define CLKID_SYS_CSI2_ADAPT 351 #define CLKID_SYS_DSPA 352 #define CLKID_SYS_PP_DMA 353 #define CLKID_SYS_PP_WRAPPER 354 #define CLKID_SYS_VPU_INTR 355 #define CLKID_SYS_CSI2_PHY0 356 #define CLKID_SYS_SAR_ADC 357 #define CLKID_SYS_PWM_J 358 #define CLKID_SYS_PWM_I 359 #define CLKID_SYS_PWM_H 360 #define CLKID_SYS_PWM_N 361 #define CLKID_SYS_PWM_M 362 #define CLKID_SYS_PWM_L 363 #define CLKID_SYS_PWM_K 364 /** * ao clk ids */ #define CLKID_AO_OSCIN_CLK 0 #define CLKID_AO_SYS_CLK 1 #define CLKID_AO_RTC_DUAL_CLKIN 2 #define CLKID_AO_RTC_DUAL_DIV 3 #define CLKID_AO_RTC_DUAL_MUX 4 #define CLKID_AO_RTC_DUAL 5 #define CLKID_AO_RTC_CLK 6 #define CLKID_AO_CECB_DUAL_CLKIN 7 #define CLKID_AO_CECB_DUAL_DIV 8 #define CLKID_AO_CECB_DUAL_MUX 9 #define CLKID_AO_CECB_DUAL 10 #define CLKID_AO_CECB_CLK 11 #define CLKID_AO_PWM_A_MUX 12 #define CLKID_AO_PWM_A_DIV 13 #define CLKID_AO_PWM_A 14 #define CLKID_AO_PWM_B_MUX 15 #define CLKID_AO_PWM_B_DIV 16 #define CLKID_AO_PWM_B 17 #define CLKID_AO_PWM_C_MUX 18 #define CLKID_AO_PWM_C_DIV 19 #define CLKID_AO_PWM_C 20 #define CLKID_AO_PWM_D_MUX 21 #define CLKID_AO_PWM_D_DIV 22 #define CLKID_AO_PWM_D 23 #define CLKID_AO_PWM_E_MUX 24 #define CLKID_AO_PWM_E_DIV 25 #define CLKID_AO_PWM_E 26 #define CLKID_AO_PWM_F_MUX 27 #define CLKID_AO_PWM_F_DIV 28 #define CLKID_AO_PWM_F 29 #define CLKID_AO_PWM_G_MUX 30 #define CLKID_AO_PWM_G_DIV 31 #define CLKID_AO_PWM_G 32 #define CLKID_AO_SYS_I3C 33 #define CLKID_AO_SYS_RTC_REG 34 #define CLKID_AO_SYS_CLKTREE 35 #define CLKID_AO_SYS_RST_CTRL 36 #define CLKID_AO_SYS_PAD 37 #define CLKID_AO_SYS_RTC_DIG 38 #define CLKID_AO_SYS_IRQ 39 #define CLKID_AO_SYS_PWRCTRL 40 #define CLKID_AO_SYS_PWM_A 41 #define CLKID_AO_SYS_PWM_B 42 #define CLKID_AO_SYS_PWM_C 43 #define CLKID_AO_SYS_PWM_D 44 #define CLKID_AO_SYS_PWM_E 45 #define CLKID_AO_SYS_PWM_F 46 #define CLKID_AO_SYS_PWM_G 47 #define CLKID_AO_SYS_I2C_M_A 48 #define CLKID_AO_SYS_I2C_M_B 49 #define CLKID_AO_SYS_I2C_M_C 50 #define CLKID_AO_SYS_I2C_M_D 51 #define CLKID_AO_SYS_SED 52 #define CLKID_AO_SYS_IR_CTRL 53 #define CLKID_AO_SYS_UART_B 54 #define CLKID_AO_SYS_UART_C 55 #define CLKID_AO_SYS_UART_D 56 #define CLKID_AO_SYS_UART_E 57 #define CLKID_AO_SYS_SPISG_0 58 #define CLKID_AO_SYS_RTC_SEC 59 #define CLKID_AO_SYS_CEC 60 #define CLKID_AO_SYS_AOCPU 61 #define CLKID_AO_SYS_SRAM 62 #define CLKID_AO_SYS_SPISG_1 63 #define CLKID_AO_SYS_SPISG_2 64 #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A9_CLKC_H */