/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A4_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_A4_CLKC_H

#define CLKID_GP0_PLL                             0
#define CLKID_HIFI_PLL                            1
#define CLKID_FCLK50M_DIV                         2
#define CLKID_FCLK50M                             3
#define CLKID_FCLK_DIV2_DIV                       4
#define CLKID_FCLK_DIV2                           5
#define CLKID_FCLK_DIV2P5_DIV                     6
#define CLKID_FCLK_DIV2P5                         7
#define CLKID_FCLK_DIV3_DIV                       8
#define CLKID_FCLK_DIV3                           9
#define CLKID_FCLK_DIV4_DIV                       10
#define CLKID_FCLK_DIV4                           11
#define CLKID_FCLK_DIV5_DIV                       12
#define CLKID_FCLK_DIV5                           13
#define CLKID_FCLK_DIV7_DIV                       14
#define CLKID_FCLK_DIV7                           15
#define CLKID_RTC_DUAL_CLKIN                      16
#define CLKID_RTC_DUAL_DIV                        17
#define CLKID_RTC_DUAL_MUX                        18
#define CLKID_RTC_DUAL                            19
#define CLKID_RTC_CLK                             20
#define CLKID_CLK_24M_IN                          21
#define CLKID_CLK_12M_DIV                         22
#define CLKID_CLK_12M                             23
#define CLKID_CLK_25M_DIV                         24
#define CLKID_CLK_25M                             25
#define CLKID_SAR_ADC_MUX                         26
#define CLKID_SAR_ADC_DIV                         27
#define CLKID_SAR_ADC                             28
#define CLKID_PWM_A_MUX                           29
#define CLKID_PWM_A_DIV                           30
#define CLKID_PWM_A                               31
#define CLKID_PWM_B_MUX                           32
#define CLKID_PWM_B_DIV                           33
#define CLKID_PWM_B                               34
#define CLKID_PWM_C_MUX                           35
#define CLKID_PWM_C_DIV                           36
#define CLKID_PWM_C                               37
#define CLKID_PWM_D_MUX                           38
#define CLKID_PWM_D_DIV                           39
#define CLKID_PWM_D                               40
#define CLKID_PWM_E_MUX                           41
#define CLKID_PWM_E_DIV                           42
#define CLKID_PWM_E                               43
#define CLKID_PWM_F_MUX                           44
#define CLKID_PWM_F_DIV                           45
#define CLKID_PWM_F                               46
#define CLKID_PWM_G_MUX                           47
#define CLKID_PWM_G_DIV                           48
#define CLKID_PWM_G                               49
#define CLKID_PWM_H_MUX                           50
#define CLKID_PWM_H_DIV                           51
#define CLKID_PWM_H                               52
#define CLKID_SPICC0_MUX                          53
#define CLKID_SPICC0_DIV                          54
#define CLKID_SPICC0                              55
#define CLKID_SPICC1_MUX                          56
#define CLKID_SPICC1_DIV                          57
#define CLKID_SPICC1                              58
#define CLKID_SD_EMMC_A_MUX                       59
#define CLKID_SD_EMMC_A_DIV                       60
#define CLKID_SD_EMMC_A                           61
#define CLKID_SD_EMMC_C_MUX                       62
#define CLKID_SD_EMMC_C_DIV                       63
#define CLKID_SD_EMMC_C                           64
#define CLKID_ETH_CLK_RMII_MUX                    65
#define CLKID_ETH_CLK_RMII_DIV                    66
#define CLKID_ETH_CLK_RMII                        67
#define CLKID_ETH_CLK125M_DIV                     68
#define CLKID_ETH_CLK125M                         69
#define CLKID_TS_DIV                              70
#define CLKID_TS                                  71
#define CLKID_VOUT_MCLK_MUX                       72
#define CLKID_VOUT_MCLK_DIV                       73
#define CLKID_VOUT_MCLK                           74
#define CLKID_VOUT_VENC_MCLK_MUX                  75
#define CLKID_VOUT_VENC_MCLK_DIV                  76
#define CLKID_VOUT_VENC_MCLK                      77
#define CLKID_AUDIO_CORE_MUX                      78
#define CLKID_AUDIO_CORE_DIV                      79
#define CLKID_AUDIO_CORE                          80
#define CLKID_GEN_MUX                             81
#define CLKID_GEN_DIV                             82
#define CLKID_GEN                                 83
#define CLKID_SYS_CLK_CTRL                        84
#define CLKID_SYS_RESET_CTRL                      85
#define CLKID_SYS_ANALOG_CTRL                     86
#define CLKID_SYS_PWR_CTRL                        87
#define CLKID_SYS_PAD_CTRL                        88
#define CLKID_SYS_SYS_CTRL                        89
#define CLKID_SYS_TS_PLL                          90
#define CLKID_SYS_DEV_ARB                         91
#define CLKID_SYS_MMC_PCLK                        92
#define CLKID_SYS_CAPU                            93
#define CLKID_SYS_MAILBOX                         94
#define CLKID_SYS_CPU_CTRL                        95
#define CLKID_SYS_JTAG_CTRL                       96
#define CLKID_SYS_IR_CTRL                         97
#define CLKID_SYS_IRQ_CTRL                        98
#define CLKID_SYS_MSR_CLK                         99
#define CLKID_SYS_ROM                             100
#define CLKID_SYS_AOCPU                           101
#define CLKID_SYS_CPU_APB                         102
#define CLKID_SYS_RSA                             103
#define CLKID_SYS_SAR_ADC                         104
#define CLKID_SYS_STARTUP                         105
#define CLKID_SYS_SECURE                          106
#define CLKID_SYS_SPIFC                           107
#define CLKID_SYS_LED_CTRL                        108
#define CLKID_SYS_ETH_PHY                         109
#define CLKID_SYS_ETH_MAC                         110
#define CLKID_SYS_GIC                             111
#define CLKID_SYS_RAMA                            112
#define CLKID_SYS_BIG_NIC                         113
#define CLKID_SYS_RAMB                            114
#define CLKID_SYS_AUDIO_TOP                       115
#define CLKID_SYS_AUDIO_VAD                       116
#define CLKID_SYS_USB                             117
#define CLKID_SYS_SD_EMMC_A                       118
#define CLKID_SYS_SD_EMMC_C                       119
#define CLKID_SYS_PWM_AB                          120
#define CLKID_SYS_PWM_CD                          121
#define CLKID_SYS_PWM_EF                          122
#define CLKID_SYS_PWM_GH                          123
#define CLKID_SYS_SPICC_1                         124
#define CLKID_SYS_SPICC_0                         125
#define CLKID_SYS_UART_A                          126
#define CLKID_SYS_UART_B                          127
#define CLKID_SYS_UART_C                          128
#define CLKID_SYS_UART_D                          129
#define CLKID_SYS_UART_E                          130
#define CLKID_SYS_I2C_M_A                         131
#define CLKID_SYS_I2C_M_B                         132
#define CLKID_SYS_I2C_M_C                         133
#define CLKID_SYS_I2C_M_D                         134
#define CLKID_SYS_RTC                             135
#define CLKID_SYS_VOUT                            136
#define CLKID_SYS_USB_CTRL                        137
#define CLKID_SYS_ACODEC                          138
#define CLKID_AXI_AUDIO_VAD                       139
#define CLKID_AXI_AUDIO_TOP                       140
#define CLKID_AXI_SYS_NIC                         141
#define CLKID_AXI_RAMA                            142
#define CLKID_AXI_CPU_DMC                         143
#define CLKID_AXI_DEV1_DMC                        144
#define CLKID_AXI_DEV0_DMC                        145
#define CLKID_AXI_DSP_DMC                         146

#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A4_CLKC_H */