/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2019 Amlogic, Inc. All rights reserved. */ #ifndef __C5_H #define __C5_H int c5_clk_init(void); void c5_clk_exit(void); int c5_aoclk_init(void); void c5_aoclk_exit(void); #define ANACTRL_FIXPLL_CTRL4 (0x0004 << 2) #define ANACTRL_GP0PLL_CTRL0 (0x0080 << 2) #define ANACTRL_GP0PLL_CTRL1 (0x0081 << 2) #define ANACTRL_GP0PLL_CTRL2 (0x0082 << 2) #define ANACTRL_GP0PLL_CTRL3 (0x0083 << 2) #define ANACTRL_HIFI0PLL_CTRL0 (0x00a0 << 2) #define ANACTRL_HIFI0PLL_CTRL1 (0x00a1 << 2) #define ANACTRL_HIFI0PLL_CTRL2 (0x00a2 << 2) #define ANACTRL_HIFI0PLL_CTRL3 (0x00a3 << 2) #define ANACTRL_CSIPLL_CTRL0 (0x00cc << 2) #define ANACTRL_CSIPLL_CTRL1 (0x00cd << 2) #define ANACTRL_CSIPLL_CTRL2 (0x00ce << 2) #define ANACTRL_CSIPLL_CTRL3 (0x00cf << 2) #define ANACTRL_CSIPLL_CTRL4 (0x00d0 << 2) #define ANACTRL_CSIPLL_CTRL5 (0x00d1 << 2) #define ANACTRL_CSIPLL_CTRL6 (0x00d2 << 2) #define ANACTRL_CSIPLL_CTRL7 (0x00d3 << 2) #define ANACTRL_CSIPLL_CTRL8 (0x00d4 << 2) #define ANACTRL_CSIPLL_CTRL9 (0x00d5 << 2) #define ANACTRL_DSIPLL_CTRL0 (0x00d8 << 2) #define ANACTRL_DSIPLL_CTRL1 (0x00d9 << 2) #define ANACTRL_DSIPLL_CTRL2 (0x00da << 2) #define ANACTRL_DSIPLL_CTRL3 (0x00db << 2) #define CLKCTRL_RTC_BY_OSCIN_CTRL0 (0x0053 << 2) #define CLKCTRL_RTC_BY_OSCIN_CTRL1 (0x0054 << 2) #define CLKCTRL_SYS_CLK_EN0_REG0 (0x008c << 2) #define CLKCTRL_SYS_CLK_EN0_REG1 (0x008d << 2) #define CLKCTRL_SYS_CLK_EN0_REG2 (0x008e << 2) #define CLKCTRL_AXI_CLK_EN0 (0x0095 << 2) #define CLKCTRL_SD_EMMC_CLK_CTRL0 (0x00a4 << 2) #define CLKCTRL_SD_EMMC_CLK_CTRL1 (0x00a5 << 2) #define CLKCTRL_PWM_CLK_C_CTRL (0x00aa << 2) #define CLKCTRL_PWM_CLK_D_CTRL (0x00ab << 2) #define CLKCTRL_PWM_CLK_E_CTRL (0x00ac << 2) #define CLKCTRL_PWM_CLK_F_CTRL (0x00ad << 2) #define CLKCTRL_PWM_CLK_G_CTRL (0x00ae << 2) #define CLKCTRL_PWM_CLK_H_CTRL (0x00af << 2) #define CLKCTRL_PWM_CLK_I_CTRL (0x00b0 << 2) #define CLKCTRL_PWM_CLK_J_CTRL (0x00b1 << 2) #define CLKCTRL_PWM_CLK_K_CTRL (0x00b2 << 2) #define CLKCTRL_PWM_CLK_L_CTRL (0x00b3 << 2) #define CLKCTRL_PWM_CLK_M_CTRL (0x00b4 << 2) #define CLKCTRL_PWM_CLK_N_CTRL (0x00b5 << 2) #define CLKCTRL_PWM_CLK_O_CTRL (0x00b6 << 2) #define CLKCTRL_PWM_CLK_P_CTRL (0x00b7 << 2) #define CLKCTRL_PWM_CLK_Q_CTRL (0x00b8 << 2) #define CLKCTRL_PWM_CLK_R_CTRL (0x00b9 << 2) #define CLKCTRL_PWM_CLK_S_CTRL (0x00ba << 2) #define CLKCTRL_PWM_CLK_T_CTRL (0x00bb << 2) #define CLKCTRL_SPISG_CLK_CTRL (0x00c0 << 2) #define CLKCTRL_SPISG_CLK_CTRL1 (0x00c1 << 2) #define CLKCTRL_SAR_CLK_CTRL0 (0x00d4 << 2) #define CLKCTRL_AMFC_CLK_CTRL (0x00d5 << 2) #define CLKCTRL_NNA_CLK_CTRL (0x00d7 << 2) #define CLKCTRL_USB_CLK_CTRL (0x00d8 << 2) #define CLKCTRL_PCIE_CLK_CTRL (0x00d9 << 2) #define CLKCTRL_CMPR_CLK_CTRL (0x00da << 2) #define CLKCTRL_DEWARPA_CLK_CTRL (0x00db << 2) #define CLKCTRL_ISP0_CLK_CTRL (0x00df << 2) #define CLKCTRL_CVE_CLK_CTRL (0x00e0 << 2) #define CLKCTRL_GLBCLK_CTRL (0x00e2 << 2) #define CLKCTRL_CAN_CLK_CTRL0 (0x00e5 << 2) #define CLKCTRL_CAN_CLK_CTRL1 (0x00e6 << 2) #define CLKCTRL_I3C_CLK_CTRL (0x00e7 << 2) #define CLKCTRL_TS_CLK_CTRL (0x00e8 << 2) #define CLKCTRL_ETH_CLK_CTRL (0x00e9 << 2) #define CLKCTRL_GEN_CLK_CTRL (0x00ea << 2) #define CLKCTRL_CLK12_24_CTRL (0x00eb << 2) #define CLKCTRL_HEVCF_CLK_CTRL (0x0110 << 2) #define CLKCTRL_HCODEC_CLK_CTRL (0x0111 << 2) #define CLKCTRL_VOUTENC_CLK_CTRL (0x0118 << 2) #define CLKCTRL_VAPBCLK_CTRL (0x011a << 2) #define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL (0x0138 << 2) #define CLKCTRL_DSI_MEAS_CLK_CTRL (0x013d << 2) #define AO_CLKCTRL_OSCIN_CTRL (0x0000 << 2) #define AO_CLKCTRL_RTC_SYS_CLK0 (0x0001 << 2) #define AO_CLKCTRL_PWM_CLK_A_CTRL (0x0007 << 2) #define AO_CLKCTRL_PWM_CLK_B_CTRL (0x0008 << 2) #define AO_CLKCTRL_ROUGH_32K_CTRL (0x0012 << 2) #define AO_CLKCTRL_PSRAM_CLK_CTRL (0x0016 << 2) /** * the gate of osc 32m is placed in the RTCCRTRL register, which * needs to be mapped separately, and the register offset needs * to be configured separately. */ #define RTCCTRL_REG_CTRL0 (0x0000 << 2) #endif /* __C5_H */